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Searched +refs:tablegen +refs:mode +refs:hook (Results 1 – 3 of 3) sorted by relevance

/external/swiftshader/third_party/LLVM/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
80 // is invalid for this mode/flavour.
252 // is invalid for this mode/flavour.
331 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
440 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.
790 // verbose-asm mode). These two values indicate the width of the first column
792 // verbose asm mode is enabled, operands will be indented to respect this.
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
25 // A string representing subtarget features that turn on this HW mode.
26 // For example, "+feat1,-feat2" will indicate that the mode is active
34 // A special mode recognized by tablegen. This mode is considered active
35 // when no other mode is active. For targets that do not use specific hw
36 // modes, this is the only mode.
49 // dependent on a HW mode. This class inherits from ValueType itself,
67 // The register size/alignment information, parameterized by a HW mode.
160 // is invalid for this mode/flavour.
211 // The register size/alignment information, parameterized by a HW mode.
[all …]
/external/llvm/include/llvm/Target/
DTarget.td1 //===- Target.td - Target Independent TableGen interface ---*- tablegen -*-===//
110 // is invalid for this mode/flavour.
301 // is invalid for this mode/flavour.
381 bit hasPostISelHook = 0; // To be *adjusted* after isel by target hook.
554 /// the TargetRegisterInfo::getPointerRegClass() hook at codegen time.