Searched refs:tckesr (Results 1 – 19 of 19) sorted by relevance
30 u8 tckesr = 5; in mctl_set_timing_params() local66 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
30 u8 tckesr = 4; in mctl_set_timing_params() local67 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
30 u8 tckesr = 4; in mctl_set_timing_params() local70 DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke), in mctl_set_timing_params()
114 u8 tckesr = 4; in auto_set_timing_para() local158 tckesr = 5; in auto_set_timing_para()180 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
114 u8 tckesr = 4; in auto_set_timing_para() local148 reg_val = (tcksrx << 24) | (tcksre << 16) | (tckesr << 8) | (tcke << 0); in auto_set_timing_para()
235 writel(MCTL_TCKESR, &mctl_ctl->tckesr); in mctl_channel_init()
31 u8 tckesr; member
76 u32 tckesr; member
73 u32 tckesr; member270 u32 tckesr; member
109 u32 tckesr; member235 u32 tckesr; member
77 u32 tckesr; member
72 u32 tckesr; member
227 .tckesr = 4, in dram_init()282 .tckesr = 4, in dram_init()
134 writel(DDRMC_CR18_TCKESR(timings->tckesr) | in ddrmc_ctrl_init_ddr3()
105 .tckesr = 4, in dram_init()
100 u32 tckesr; /* 0x140 */ member
124 .tckesr = 4, in dram_init()
86 tckesr
518 pctl_timing->tckesr = pctl_timing->tcke + 1; /* JESD-79: tCKE + 1tCK */ in pctl_calc_timings()