Searched refs:tgcr (Results 1 – 4 of 4) sorted by relevance
| /external/u-boot/arch/arm/mach-davinci/ |
| D | timer.c | 41 writel(0x0, &timer->tgcr); in timer_init()
42 writel(0x06 | ((TIM_CLK_DIV - 1) << 8), &timer->tgcr); in timer_init()
108 writel(0x0, &wdttimer->tgcr); in davinci_hw_watchdog_enable()
110 writel(0x08 | 0x03 | ((TIM_CLK_DIV - 1) << 8), &wdttimer->tgcr); in davinci_hw_watchdog_enable()
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| D | reset.c | 18 writel(0x08, &wdttimer->tgcr); in reset_cpu()
19 writel(readl(&wdttimer->tgcr) | 0x03, &wdttimer->tgcr); in reset_cpu()
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| /external/u-boot/arch/arm/mach-davinci/include/mach/ |
| D | timer_defs.h | 19 u_int32_t tgcr; member
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| /external/u-boot/ |
| D | README | 4602 …tgcr @ 0xfff00980, tmr @ 0xfff00990, trr @ 0xfff00994, tcr @ 0xfff00998, tcn @ 0xfff0099c, ter @ 0…
4609 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0xef6, ter=0x0
4612 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x2ad4, ter=0x0
4615 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x1efc, ter=0x0
4618 tgcr=0x1, tmr=0xff1c, trr=0x3d09, tcr=0x0, tcn=0x169d, ter=0x0
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