Searched refs:timing_cfg_1 (Results 1 – 25 of 49) sorted by relevance
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/external/u-boot/board/freescale/corenet_ds/ |
D | p4080ds_ddr.c | 89 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 121 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 153 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, 185 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_900, 217 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, 249 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1000, 281 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200, 313 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1200,
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/external/u-boot/drivers/ddr/fsl/ |
D | mpc85xx_ddr_gen1.c | 45 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
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D | mpc86xx_ddr.c | 53 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
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D | mpc85xx_ddr_gen2.c | 68 out_be32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
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D | arm_ddr_gen3.c | 93 ddr_out32(&ddr->timing_cfg_1, regs->timing_cfg_1); in fsl_ddr_set_memctl_regs()
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/external/u-boot/board/freescale/bsc9132qds/ |
D | spl_minimal.c | 30 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init() 50 __raw_writel(CONFIG_SYS_DDR_TIMING_1_1333, &ddr->timing_cfg_1); in sdram_init()
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D | ddr.c | 23 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 50 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_1333,
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/external/u-boot/board/sbc8641d/ |
D | sbc8641d.c | 111 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram() 142 ddr->timing_cfg_1 = CONFIG_SYS_DDR2_TIMING_1; in fixed_sdram()
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/external/u-boot/board/freescale/p1010rdb/ |
D | ddr.c | 26 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800, 53 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_667,
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/external/u-boot/board/freescale/mpc8349emds/ |
D | mpc8349emds.c | 104 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram() 129 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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/external/u-boot/board/freescale/mpc8349itx/ |
D | mpc8349itx.c | 59 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram() 73 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1); in fixed_sdram()
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/external/u-boot/board/freescale/p1_twr/ |
D | ddr.c | 32 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()
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/external/u-boot/board/socrates/ |
D | sdram.c | 38 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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/external/u-boot/board/freescale/ls1043ardb/ |
D | ddr.h | 61 .timing_cfg_1 = 0xBBB48C42,
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/external/u-boot/board/gdsys/mpc8308/ |
D | sdram.c | 49 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
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/external/u-boot/board/sbc8548/ |
D | ddr.c | 106 out_be32(&ddr->timing_cfg_1, 0x38377322); in fixed_sdram()
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/external/u-boot/board/mpc8308_p1m/ |
D | sdram.c | 44 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
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/external/u-boot/board/freescale/mpc8308rdb/ |
D | sdram.c | 48 out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); in fixed_sdram()
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/external/u-boot/board/freescale/mpc8315erdb/ |
D | sdram.c | 65 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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/external/u-boot/board/freescale/bsc9131rdb/ |
D | spl_minimal.c | 33 __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); in sdram_init()
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D | ddr.c | 24 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1_800,
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/external/u-boot/board/freescale/mpc8313erdb/ |
D | sdram.c | 74 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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/external/u-boot/board/freescale/mpc832xemds/ |
D | mpc832xemds.c | 137 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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/external/u-boot/board/Arcturus/ucp1020/ |
D | ddr.c | 92 .timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1, in fixed_sdram()
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/external/u-boot/board/freescale/mpc8641hpcn/ |
D | mpc8641hpcn.c | 75 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1; in fixed_sdram()
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