Searched refs:timing_cfg_7 (Results 1 – 6 of 6) sorted by relevance
90 .timing_cfg_7 = 0x13300000,
53 u32 timing_cfg_7; /* SDRAM Timing Configuration 7 */ member
280 unsigned int timing_cfg_7; member
162 ddr_out32(&ddr->timing_cfg_7, regs->timing_cfg_7); in fsl_ddr_set_memctl_regs()
2036 ddr->timing_cfg_7 = (0 in set_timing_cfg_7()2043 debug("FSLDDR: timing_cfg_7 = 0x%08x\n", ddr->timing_cfg_7); in set_timing_cfg_7()
662 CFG_REGS(timing_cfg_7), in print_fsl_memctl_config_regs()753 CFG_REGS(timing_cfg_7), in fsl_ddr_regs_edit()