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Searched refs:tmrw (Results 1 – 5 of 5) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/dram_timings/
Dlpddr3_stock.c24 u8 tmrw = 5; in mctl_set_timing_params() local
61 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
Dddr2_v3s.c24 u8 tmrw = 0; in mctl_set_timing_params() local
62 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
Dddr3_1333.c24 u8 tmrw = 0; in mctl_set_timing_params() local
65 writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod), in mctl_set_timing_params()
/external/u-boot/arch/arm/mach-sunxi/
Ddram_sun8i_a83t.c108 u8 tmrw = 0; in auto_set_timing_para() local
156 tmrw = 5; in auto_set_timing_para()
176 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()
Ddram_sun8i_a33.c108 u8 tmrw = 0; in auto_set_timing_para() local
144 reg_val = (tmrw << 16) | (tmrd << 12) | (tmod << 0); in auto_set_timing_para()