| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 277 define i32 @uhasx(i32 %a, i32 %b) nounwind {
278 ; CHECK-LABEL: uhasx
279 ; CHECK: uhasx r0, r0, r1
280 %tmp = call i32 @llvm.arm.uhasx(i32 %a, i32 %b)
462 declare i32 @llvm.arm.uhasx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 82 M(uhasx) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 81 M(uhasx) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 1090 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
1095 0xa1,0xfa,0x65,0xf4 = uhasx r4, r1, r5
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| D | basic-arm-instructions.s.cs | 911 0x32,0x4f,0x78,0xe6 = uhasx r4, r8, r2
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2866 uhasx r4, r1, r5
2877 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
2882 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
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| D | basic-arm-instructions.s | 2345 uhasx r4, r8, r2
2348 @ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3419 uhasx r4, r1, r5
3430 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
3435 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
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| D | basic-arm-instructions.s | 3265 uhasx r4, r8, r2
3268 @ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6]
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| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3363 uhasx r4, r1, r5
3374 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
3379 @ CHECK: uhasx r4, r1, r5 @ encoding: [0xa1,0xfa,0x65,0xf4]
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| D | basic-arm-instructions.s | 3263 uhasx r4, r8, r2
3266 @ CHECK: uhasx r4, r8, r2 @ encoding: [0x32,0x4f,0x78,0xe6]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3646 void uhasx(Condition cond, Register rd, Register rn, Register rm);
3647 void uhasx(Register rd, Register rn, Register rm) { uhasx(al, rd, rn, rm); } in uhasx() function
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| D | disasm-aarch32.h | 1377 void uhasx(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2083 # CHECK: uhasx r4, r8, r2
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| D | thumb2.txt | 2236 # CHECK: uhasx r4, r1, r5
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2387 # CHECK: uhasx r4, r1, r5
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| D | basic-arm-instructions.txt | 2256 # CHECK: uhasx r4, r8, r2
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2256 # CHECK: uhasx r4, r8, r2
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| D | thumb2.txt | 2387 # CHECK: uhasx r4, r1, r5
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| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3209 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
4985 def : MnemonicAlias<"uhaddsubx", "uhasx">;
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| D | ARMInstrThumb2.td | 1976 def t2UHASX : T2I_pam<0b010, 0b0110, "uhasx">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3755 def UHASX : AAIIntrinsic<0b01100111, 0b11110011, "uhasx", int_arm_uhasx>;
5995 def : MnemonicAlias<"uhaddsubx", "uhasx">;
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| D | ARMInstrThumb2.td | 2249 def t2UHASX : T2I_pam_intrinsics<0b010, 0b0110, "uhasx", int_arm_uhasx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3610 def UHASX : AAI<0b01100111, 0b11110011, "uhasx">;
5695 def : MnemonicAlias<"uhaddsubx", "uhasx">;
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| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1370 Mnemonic = "uhasx"; // "uhaddsubx"
7766 "uasx\004ubfx\003udf\004udiv\007uhadd16\006uhadd8\005uhasx\005uhsax\007u"
9045 …{ 1582 /* uhasx */, ARM::t2UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThumb2|F…
9046 …{ 1582 /* uhasx */, ARM::UHASX, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, { MCK…
|