| /external/swiftshader/third_party/llvm-7.0/llvm/docs/CommandGuide/ |
| D | llvm-exegesis.rst | 41 $ llvm-exegesis -mode=uops -opcode-name=ADD64rr
81 Assuming you have a set of benchmarked instructions (either latency or uops) as
143 .. option:: -mode=[latency|uops|analysis]
154 File to read (`analysis` mode) or write (`latency`/`uops` modes) benchmark
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryo.td | 17 // uops. Now, the latency spreadsheet has information based on fragmented uops,
21 let IssueWidth = 5; // 5-wide issue for expanded uops
|
| D | AArch64SchedFalkor.td | 20 let IssueWidth = 8; // 8 uops are dispatched per cycle.
|
| D | AArch64SchedExynosM3.td | 21 let IssueWidth = 6; // Up to 6 uops per cycle.
|
| D | AArch64SchedExynosM1.td | 21 let IssueWidth = 4; // Up to 4 uops per cycle.
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64SchedKryo.td | 17 // uops. Now, the latency spreadsheet has information based on fragmented uops,
21 let IssueWidth = 5; // 5-wide issue for expanded uops
|
| D | AArch64SchedM1.td | 21 let IssueWidth = 4; // Up to 4 uops per cycle.
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMScheduleA8.td | 155 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
160 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
166 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
171 [1, 1, 3], [], -1>, // dynamic uops
177 [1, 1, 3], [], -1>, // dynamic uops
233 [], [], -1>, // dynamic uops
238 [2], [], -1>, // dynamic uops
400 [1, 1, 1, 2], [], -1>, // dynamic uops
408 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
428 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
|
| D | ARMScheduleA9.td | 288 -1>, // dynamic uops
297 -1>, // dynamic uops
307 -1>, // dynamic uops
316 -1>, // dynamic uops
326 -1>, // dynamic uops
421 [], [], -1>, // dynamic uops
428 [2], [], -1>, // dynamic uops
726 [1, 1, 1, 1], [], -1>, // dynamic uops
736 [2, 1, 1, 1], [], -1>, // dynamic uops
764 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMScheduleA8.td | 155 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
160 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
166 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
171 [1, 1, 3], [], -1>, // dynamic uops
177 [1, 1, 3], [], -1>, // dynamic uops
233 [], [], -1>, // dynamic uops
238 [2], [], -1>, // dynamic uops
400 [1, 1, 1, 2], [], -1>, // dynamic uops
408 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
428 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
|
| D | ARMScheduleA9.td | 288 -1>, // dynamic uops
297 -1>, // dynamic uops
307 -1>, // dynamic uops
316 -1>, // dynamic uops
326 -1>, // dynamic uops
421 [], [], -1>, // dynamic uops
428 [2], [], -1>, // dynamic uops
726 [1, 1, 1, 1], [], -1>, // dynamic uops
736 [2, 1, 1, 1], [], -1>, // dynamic uops
764 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/SLPVectorizer/ARM/ |
| D | memory.ll | 5 ; On swift unaligned <2 x double> stores need 4uops and it is there for cheaper
|
| /external/llvm/test/Transforms/SLPVectorizer/ARM/ |
| D | memory.ll | 5 ; On swift unaligned <2 x double> stores need 4uops and it is there for cheaper
|
| /external/llvm/include/llvm/Target/ |
| D | TargetItinerary.td | 112 list<Bypass> bypasses = [], int uops = 1> {
114 int NumMicroOps = uops;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/Target/ |
| D | TargetItinerary.td | 112 list<Bypass> bypasses = [], int uops = 1> {
114 int NumMicroOps = uops;
|
| D | TargetSchedule.td | 545 // Each ProcResourceUnits can define how to measure issued uops by defining
549 // The resource units on which uops are issued.
|
| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 281 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
282 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
|
| /external/google-breakpad/src/third_party/libdisasm/ |
| D | ia32_insn.h | 495 unsigned char uops; /* uops per insn */
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonMachineScheduler.cpp | 340 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
341 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
|
| /external/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 315 // These instructions are split across multiple uops (in different pipelines)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/docs/ |
| D | ReleaseNotes.rst | 43 properties (latency/uops) and provides a principled way to edit scheduling
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ScheduleZnver1.td | 301 …esFpuPair<WriteFRnd, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
302 …esFpuPair<WriteFRndY, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsScheduleP5600.td | 509 // These instructions are split across multiple uops (in different pipelines)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1942 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
1943 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { in checkHazard()
|
| /external/llvm/lib/CodeGen/ |
| D | MachineScheduler.cpp | 1867 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
1868 if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) { in checkHazard()
|