/external/llvm/test/MC/Disassembler/ARM/ |
D | unpredictable-UQADD8-arm.txt | 15 # CHECK: uqadd8 r5, r6, pc
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D | arm-tests.txt | 336 # CHECK: uqadd8 r5, r6, r7
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D | thumb2.txt | 2455 # CHECK: uqadd8 r3, r4, r8
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D | basic-arm-instructions.txt | 2320 # CHECK: uqadd8 r3, r4, r8
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | unpredictable-UQADD8-arm.txt | 15 # CHECK: uqadd8 r5, r6, pc
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D | arm-tests.txt | 336 # CHECK: uqadd8 r5, r6, r7
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D | basic-arm-instructions.txt | 2320 # CHECK: uqadd8 r3, r4, r8
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D | thumb2.txt | 2455 # CHECK: uqadd8 r3, r4, r8
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | acle-intrinsics.ll | 142 define i32 @uqadd8(i32 %a, i32 %b) nounwind { 143 ; CHECK-LABEL: uqadd8 144 ; CHECK: uqadd8 r0, r0, r1 145 %tmp = call i32 @llvm.arm.uqadd8(i32 %a, i32 %b) 441 declare i32 @llvm.arm.uqadd8(i32, i32) nounwind
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | arm-tests.txt | 294 # CHECK: uqadd8 r5, r6, r7
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D | basic-arm-instructions.txt | 2147 # CHECK: uqadd8 r3, r4, r8
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D | thumb2.txt | 2304 # CHECK: uqadd8 r3, r4, r8
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/external/vixl/test/aarch32/ |
D | test-assembler-cond-rd-rn-rm-a32.cc | 87 M(uqadd8) \
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D | test-assembler-cond-rd-rn-rm-t32.cc | 86 M(uqadd8) \
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 929 0x98,0x3f,0x64,0xe6 = uqadd8 r3, r4, r8
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D | basic-thumb2-instructions.s.cs | 1115 0x84,0xfa,0x58,0xf3 = uqadd8 r3, r4, r8
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 2409 uqadd8 r3, r4, r8 2415 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6]
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D | basic-thumb2-instructions.s | 2945 uqadd8 r3, r4, r8 2951 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x84,0xfa,0x58,0xf3]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3695 void uqadd8(Condition cond, Register rd, Register rn, Register rm); 3696 void uqadd8(Register rd, Register rn, Register rm) { uqadd8(al, rd, rn, rm); } in uqadd8() function
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D | disasm-aarch32.h | 1402 void uqadd8(Condition cond, Register rd, Register rn, Register rm);
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | basic-thumb2-instructions.s | 3498 uqadd8 r3, r4, r8 3504 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x84,0xfa,0x58,0xf3]
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D | basic-arm-instructions.s | 3329 uqadd8 r3, r4, r8 3335 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6]
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/external/llvm/test/MC/ARM/ |
D | basic-arm-instructions.s | 3327 uqadd8 r3, r4, r8 3333 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x98,0x3f,0x64,0xe6]
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D | basic-thumb2-instructions.s | 3442 uqadd8 r3, r4, r8 3448 @ CHECK: uqadd8 r3, r4, r8 @ encoding: [0x84,0xfa,0x58,0xf3]
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 1947 def t2UQADD8 : T2I_pam<0b000, 0b0101, "uqadd8">;
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