| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 305 define i32 @uqasx(i32 %a, i32 %b) nounwind {
306 ; CHECK-LABEL: uqasx
307 ; CHECK: uqasx r0, r0, r1
308 %tmp = call i32 @llvm.arm.uqasx(i32 %a, i32 %b)
466 declare i32 @llvm.arm.uqasx(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 88 M(uqasx) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 87 M(uqasx) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-thumb2-instructions.s.cs | 1119 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3
1124 0xa2,0xfa,0x53,0xf1 = uqasx r1, r2, r3
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| D | basic-arm-instructions.s.cs | 931 0x31,0x2f,0x64,0xe6 = uqasx r2, r4, r1
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 2960 uqasx r1, r2, r3
2972 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
2978 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
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| D | basic-arm-instructions.s | 2422 uqasx r2, r4, r1
2425 @ CHECK: uqasx r2, r4, r1 @ encoding: [0x31,0x2f,0x64,0xe6]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3513 uqasx r1, r2, r3
3525 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
3531 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
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| D | basic-arm-instructions.s | 3342 uqasx r2, r4, r1
3345 @ CHECK: uqasx r2, r4, r1 @ encoding: [0x31,0x2f,0x64,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3457 uqasx r1, r2, r3
3469 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
3475 @ CHECK: uqasx r1, r2, r3 @ encoding: [0xa2,0xfa,0x53,0xf1]
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| D | basic-arm-instructions.s | 3340 uqasx r2, r4, r1
3343 @ CHECK: uqasx r2, r4, r1 @ encoding: [0x31,0x2f,0x64,0xe6]
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3698 void uqasx(Condition cond, Register rd, Register rn, Register rm);
3699 void uqasx(Register rd, Register rn, Register rm) { uqasx(al, rd, rn, rm); } in uqasx() function
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| D | disasm-aarch32.h | 1404 void uqasx(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2160 # CHECK: uqasx r2, r4, r1
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| D | thumb2.txt | 2319 # CHECK: uqasx r1, r2, r3
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| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2470 # CHECK: uqasx r1, r2, r3
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| D | basic-arm-instructions.txt | 2333 # CHECK: uqasx r2, r4, r1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2333 # CHECK: uqasx r2, r4, r1
|
| D | thumb2.txt | 2470 # CHECK: uqasx r1, r2, r3
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3181 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
4989 def : MnemonicAlias<"uqaddsubx", "uqasx">;
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| D | ARMInstrThumb2.td | 1948 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3729 def UQASX : AAIIntrinsic<0b01100110, 0b11110011, "uqasx", int_arm_uqasx>;
5999 def : MnemonicAlias<"uqaddsubx", "uqasx">;
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| D | ARMInstrThumb2.td | 2209 def t2UQASX : T2I_pam_intrinsics<0b010, 0b0101, "uqasx", int_arm_uqasx>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.td | 3582 def UQASX : AAI<0b01100110, 0b11110011, "uqasx">;
5699 def : MnemonicAlias<"uqaddsubx", "uqasx">;
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| D | ARMInstrThumb2.td | 2153 def t2UQASX : T2I_pam<0b010, 0b0101, "uqasx">;
|