| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | acle-intrinsics.ll | 319 define i32 @uqsub16(i32 %a, i32 %b) nounwind {
320 ; CHECK-LABEL: uqsub16
321 ; CHECK: uqsub16 r0, r0, r1
322 %tmp = call i32 @llvm.arm.uqsub16(i32 %a, i32 %b)
468 declare i32 @llvm.arm.uqsub16(i32, i32) nounwind
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| /external/vixl/test/aarch32/ |
| D | test-assembler-cond-rd-rn-rm-a32.cc | 90 M(uqsub16) \
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| D | test-assembler-cond-rd-rn-rm-t32.cc | 89 M(uqsub16) \
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| /external/capstone/suite/MC/ARM/ |
| D | basic-arm-instructions.s.cs | 935 0x73,0x1f,0x65,0xe6 = uqsub16 r1, r5, r3
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| D | basic-thumb2-instructions.s.cs | 1130 0xd9,0xfa,0x57,0xf1 = uqsub16 r1, r9, r7
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| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | basic-arm-instructions.s | 2442 uqsub16 r1, r5, r3
2447 @ CHECK: uqsub16 r1, r5, r3 @ encoding: [0x73,0x1f,0x65,0xe6]
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| D | basic-thumb2-instructions.s | 2989 uqsub16 r1, r9, r7
2995 @ CHECK: uqsub16 r1, r9, r7 @ encoding: [0xd9,0xfa,0x57,0xf1]
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| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 3704 void uqsub16(Condition cond, Register rd, Register rn, Register rm);
3705 void uqsub16(Register rd, Register rn, Register rm) { in uqsub16() function
3706 uqsub16(al, rd, rn, rm); in uqsub16()
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| D | disasm-aarch32.h | 1408 void uqsub16(Condition cond, Register rd, Register rn, Register rm);
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | basic-thumb2-instructions.s | 3542 uqsub16 r1, r9, r7
3548 @ CHECK: uqsub16 r1, r9, r7 @ encoding: [0xd9,0xfa,0x57,0xf1]
|
| D | basic-arm-instructions.s | 3362 uqsub16 r1, r5, r3
3367 @ CHECK: uqsub16 r1, r5, r3 @ encoding: [0x73,0x1f,0x65,0xe6]
|
| /external/llvm/test/MC/ARM/ |
| D | basic-arm-instructions.s | 3360 uqsub16 r1, r5, r3
3365 @ CHECK: uqsub16 r1, r5, r3 @ encoding: [0x73,0x1f,0x65,0xe6]
|
| D | basic-thumb2-instructions.s | 3486 uqsub16 r1, r9, r7
3492 @ CHECK: uqsub16 r1, r9, r7 @ encoding: [0xd9,0xfa,0x57,0xf1]
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2180 # CHECK: uqsub16 r1, r5, r3
|
| D | thumb2.txt | 2336 # CHECK: uqsub16 r1, r9, r7
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | thumb2.txt | 2487 # CHECK: uqsub16 r1, r9, r7
|
| D | basic-arm-instructions.txt | 2353 # CHECK: uqsub16 r1, r5, r3
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | basic-arm-instructions.txt | 2353 # CHECK: uqsub16 r1, r5, r3
|
| D | thumb2.txt | 2487 # CHECK: uqsub16 r1, r9, r7
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 1950 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
|
| D | ARMInstrInfo.td | 3183 def UQSUB16 : AAI<0b01100110, 0b11110111, "uqsub16">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2211 def t2UQSUB16 : T2I_pam_intrinsics<0b101, 0b0101, "uqsub16", int_arm_uqsub16>;
|
| D | ARMInstrInfo.td | 3725 def UQSUB16 : AAIIntrinsic<0b01100110, 0b11110111, "uqsub16", int_arm_uqsub16>;
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrThumb2.td | 2155 def t2UQSUB16 : T2I_pam<0b101, 0b0101, "uqsub16">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 7768 "sx\005uqsax\007uqsub16\006uqsub8\005usad8\006usada8\004usat\006usat16\004"
9069 …{ 1654 /* uqsub16 */, ARM::t2UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsThum…
9070 …{ 1654 /* uqsub16 */, ARM::UQSUB16, Convert__Reg1_1__Reg1_2__Reg1_3__CondCode2_0, Feature_IsARM, {…
|