| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 198 ;CHECK: ursqrte.2s
200 %tmp3 = call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
206 ;CHECK: ursqrte.4s
208 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
212 declare <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32>) nounwind readnone
213 declare <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32>) nounwind readnone
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | arm64-vsqrt.ll | 198 ;CHECK: ursqrte.2s
200 %tmp3 = call <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32> %tmp1)
206 ;CHECK: ursqrte.4s
208 %tmp3 = call <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32> %tmp1)
212 declare <2 x i32> @llvm.aarch64.neon.ursqrte.v2i32(<2 x i32>) nounwind readnone
213 declare <4 x i32> @llvm.aarch64.neon.ursqrte.v4i32(<4 x i32>) nounwind readnone
|
| /external/capstone/suite/MC/AArch64/ |
| D | neon-simd-misc.s.cs | 197 0x06,0xc9,0xa1,0x6e = ursqrte v6.4s, v8.4s
198 0x04,0xc8,0xa1,0x2e = ursqrte v4.2s, v0.2s
|
| /external/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 676 ursqrte v6.4s, v8.4s
677 ursqrte v4.2s, v0.2s
|
| D | neon-diagnostics.s | 5947 ursqrte v0.16b, v31.16b
5948 ursqrte v2.8h, v4.8h
5949 ursqrte v1.8b, v9.8b
5950 ursqrte v13.4h, v21.4h
5951 ursqrte v1.2d, v9.2d
|
| D | arm64-advsimd.s | 605 ursqrte.2s v0, v0
655 ; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | neon-simd-misc.s | 676 ursqrte v6.4s, v8.4s
677 ursqrte v4.2s, v0.2s
|
| D | neon-diagnostics.s | 5887 ursqrte v0.16b, v31.16b
5888 ursqrte v2.8h, v4.8h
5889 ursqrte v1.8b, v9.8b
5890 ursqrte v13.4h, v21.4h
5891 ursqrte v1.2d, v9.2d
|
| D | arm64-advsimd.s | 605 ursqrte.2s v0, v0
655 ; CHECK: ursqrte.2s v0, v0 ; encoding: [0x00,0xc8,0xa1,0x2e]
|
| /external/v8/src/arm64/ |
| D | macro-assembler-arm64.h | 349 V(ursqrte, Ursqrte) \
|
| D | simulator-arm64.h | 1993 LogicVRegister ursqrte(VectorFormat vform, LogicVRegister dst,
|
| D | assembler-arm64.h | 2701 void ursqrte(const VRegister& vd, const VRegister& vn);
|
| D | simulator-logic-arm64.cc | 4064 LogicVRegister Simulator::ursqrte(VectorFormat vform, LogicVRegister dst, in ursqrte() function in v8::internal::Simulator
|
| D | simulator-arm64.cc | 3651 ursqrte(fpf, rd, rn); in VisitNEON2RegMisc()
|
| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.h | 2964 LogicVRegister ursqrte(VectorFormat vform,
|
| D | assembler-aarch64.h | 2884 void ursqrte(const VRegister& vd, const VRegister& vn);
|
| D | macro-assembler-aarch64.h | 2741 V(ursqrte, Ursqrte) \
|
| /external/vixl/test/test-trace-reference/ |
| D | log-disasm | 2064 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s
2065 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s
|
| D | log-disasm-colour | 2064 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s
2065 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s
|
| D | log-cpufeatures-custom | 2063 0x~~~~~~~~~~~~~~~~ 2ea1ca14 ursqrte v20.2s, v16.2s ### {NEON} ###
2064 0x~~~~~~~~~~~~~~~~ 6ea1c91c ursqrte v28.4s, v8.4s ### {NEON} ###
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 2406 __ ursqrte(v20.V2S(), v16.V2S()); in GenerateTestSequenceNEON() local
2407 __ ursqrte(v28.V4S(), v8.V4S()); in GenerateTestSequenceNEON() local
|
| D | test-simulator-aarch64.cc | 4807 DEFINE_TEST_NEON_2SAME_2S_4S(ursqrte, Basic) in DEFINE_TEST_NEON_2DIFF_FP_SCALAR_SD()
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 4095 void ursqrte(const VRegister& vd, const VRegister& vn)
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 504 # CHECK: ursqrte.2s v0, v0
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | arm64-advsimd.txt | 504 # CHECK: ursqrte.2s v0, v0
|