/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
D | acle-intrinsics.ll | 50 define i32 @usat16(i32 %a) nounwind { 51 ; CHECK-LABEL: usat16 52 ; CHECK: usat16 r0, #0, r0 53 ; CHECK: usat16 r0, #15, r0 54 %tmp = call i32 @llvm.arm.usat16(i32 %a, i32 0) 55 %tmp2 = call i32 @llvm.arm.usat16(i32 %tmp, i32 15) 426 declare i32 @llvm.arm.usat16(i32, i32) nounwind
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
D | thumb-tests.txt | 287 # CHECK: usat16 r4, #10, r1
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D | basic-arm-instructions.txt | 2397 # CHECK: usat16 r2, #2, r7 2398 # CHECK: usat16 r3, #15, r5
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D | thumb2.txt | 2532 # CHECK: usat16 r2, #2, r7 2533 # CHECK: usat16 r3, #15, r5
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/external/llvm/test/MC/Disassembler/ARM/ |
D | thumb-tests.txt | 287 # CHECK: usat16 r4, #10, r1
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D | thumb2.txt | 2532 # CHECK: usat16 r2, #2, r7 2533 # CHECK: usat16 r3, #15, r5
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D | basic-arm-instructions.txt | 2397 # CHECK: usat16 r2, #2, r7 2398 # CHECK: usat16 r3, #15, r5
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/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
D | thumb-tests.txt | 284 # CHECK: usat16 r4, #10, r1
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D | basic-arm-instructions.txt | 2224 # CHECK: usat16 r2, #2, r7 2225 # CHECK: usat16 r3, #15, r5
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D | thumb2.txt | 2381 # CHECK: usat16 r2, #2, r7 2382 # CHECK: usat16 r3, #15, r5
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/external/capstone/suite/MC/ARM/ |
D | basic-arm-instructions.s.cs | 948 0x37,0x2f,0xe2,0xe6 = usat16 r2, #2, r7 949 0x35,0x3f,0xef,0xe6 = usat16 r3, #15, r5
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D | basic-thumb2-instructions.s.cs | 1143 0xa7,0xf3,0x02,0x02 = usat16 r2, #2, r7 1144 0xa5,0xf3,0x0f,0x03 = usat16 r3, #15, r5
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/external/swiftshader/third_party/LLVM/test/MC/ARM/ |
D | basic-arm-instructions.s | 2486 usat16 r2, #2, r7 2487 usat16 r3, #15, r5 2489 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6] 2490 @ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
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D | basic-thumb2-instructions.s | 3034 usat16 r2, #2, r7 3035 usat16 r3, #15, r5 3037 @ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02] 3038 @ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03]
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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
D | basic-thumb2-instructions.s | 3587 usat16 r2, #2, r7 3588 usat16 r3, #15, r5 3590 @ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02] 3591 @ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03]
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D | basic-arm-instructions.s | 3406 usat16 r2, #2, r7 3407 usat16 r3, #15, r5 3409 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6] 3410 @ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
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/external/llvm/test/MC/ARM/ |
D | basic-arm-instructions.s | 3404 usat16 r2, #2, r7 3405 usat16 r3, #15, r5 3407 @ CHECK: usat16 r2, #2, r7 @ encoding: [0x37,0x2f,0xe2,0xe6] 3408 @ CHECK: usat16 r3, #15, r5 @ encoding: [0x35,0x3f,0xef,0xe6]
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D | basic-thumb2-instructions.s | 3531 usat16 r2, #2, r7 3532 usat16 r3, #15, r5 3534 @ CHECK: usat16 r2, #2, r7 @ encoding: [0xa7,0xf3,0x02,0x02] 3535 @ CHECK: usat16 r3, #15, r5 @ encoding: [0xa5,0xf3,0x0f,0x03]
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/external/vixl/src/aarch32/ |
D | assembler-aarch32.h | 3726 void usat16(Condition cond, Register rd, uint32_t imm, Register rn); 3727 void usat16(Register rd, uint32_t imm, Register rn) { in usat16() function 3728 usat16(al, rd, imm, rn); in usat16()
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D | disasm-aarch32.h | 1419 void usat16(Condition cond, Register rd, uint32_t imm, Register rn);
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2072 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
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D | ARMInstrInfo.td | 3297 NoItinerary, "usat16", "\t$Rd, $sat_imm, $Rn", []> {
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2336 "usat16", "\t$Rd, $sat_imm, $Rn">,
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/external/llvm/lib/Target/ARM/ |
D | ARMInstrThumb2.td | 2277 "usat16", "\t$Rd, $sat_imm, $Rn", []>,
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/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
D | ARMGenAsmMatcher.inc | 7768 "sx\005uqsax\007uqsub16\006uqsub8\005usad8\006usada8\004usat\006usat16\004" 9081 …{ 1687 /* usat16 */, ARM::t2USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsTh… 9082 …{ 1687 /* usat16 */, ARM::USAT16, Convert__Reg1_1__Imm0_151_2__Reg1_3__CondCode2_0, Feature_IsARM|…
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