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Searched refs:ushll (Results 1 – 25 of 69) sorted by relevance

123

/external/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll11 ; CHECK-NEXT: ushll.8h v0, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
49 ; CHECK-NEXT: ushll.4s v0, v0, #0
66 ; CHECK-NEXT: ushll.4s v0, v0, #0
83 ; CHECK-NEXT: ushll.8h v0, v0, #0
85 ; CHECK-NEXT: ushll.4s v0, v0, #0
108 ; CHECK-NEXT: ushll.2d v0, v0, #0
125 ; CHECK-NEXT: ushll.4s v0, v0, #0
127 ; CHECK-NEXT: ushll.2d v0, v0, #0
Dneon-shift-left-long.ll29 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
37 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
45 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
128 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
135 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
142 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
198 ; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
Dcomplex-int-to-fp.ll24 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
Darm64-vbitwise.ll32 ;CHECK: ushll.8h
48 ;CHECK: ushll.4s
64 ;CHECK: ushll.2d
Dfast-isel-cmp-vec.ll47 ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
63 ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
Darm64-extend-int-to-fp.ll5 ; CHECK: ushll.4s v0, v0, #0
Darm64-vector-ext.ll6 ;CHECK: ushll.4s v0, v0, #0
Darm64-vselect.ll7 ; ushll.4s v0, v0, #0
Dfp16-v8-instructions.ll311 ; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
313 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
327 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
Dfdiv_combine.ll75 ; CHECK: ushll.4s v0, v0, #0
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-subvector-extend.ll11 ; CHECK-NEXT: ushll.8h v0, v0, #0
28 ; CHECK-NEXT: ushll.8h v0, v0, #0
49 ; CHECK-NEXT: ushll.4s v0, v0, #0
66 ; CHECK-NEXT: ushll.4s v0, v0, #0
83 ; CHECK-NEXT: ushll.8h v0, v0, #0
85 ; CHECK-NEXT: ushll.4s v0, v0, #0
108 ; CHECK-NEXT: ushll.2d v0, v0, #0
125 ; CHECK-NEXT: ushll.4s v0, v0, #0
127 ; CHECK-NEXT: ushll.2d v0, v0, #0
Dneon-shift-left-long.ll29 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #3
37 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #9
45 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #19
128 ; CHECK: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
135 ; CHECK: ushll {{v[0-9]+}}.4s, {{v[0-9]+}}.4h, #0
142 ; CHECK: ushll {{v[0-9]+}}.2d, {{v[0-9]+}}.2s, #0
198 ; CHECK-NEXT: ushll {{v[0-9]+}}.8h, {{v[0-9]+}}.8b, #0
Dcomplex-int-to-fp.ll24 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], v0, #0
45 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
66 ; CHECK: ushll.2d [[VAL64:v[0-9]+]], [[VAL32]], #0
139 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
159 ; CHECK: ushll.4s [[VAL32:v[0-9]+]], v0, #0
Darm64-vbitwise.ll32 ;CHECK: ushll.8h
48 ;CHECK: ushll.4s
64 ;CHECK: ushll.2d
Dfast-isel-cmp-vec.ll47 ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
63 ; CHECK-NEXT: ushll.4s v0, [[ZEXT]], #0
Darm64-extend-int-to-fp.ll5 ; CHECK: ushll.4s v0, v0, #0
Darm64-vector-ext.ll6 ;CHECK: ushll.4s v0, v0, #0
Darm64-vselect.ll7 ; ushll.4s v0, v0, #0
Dfdiv_combine.ll75 ; CHECK: ushll.4s v0, v0, #0
Dfp16-v8-instructions.ll335 ; CHECK-NEXT: ushll v[[REG1:[0-9]+]].8h, v0.8b, #0
337 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v[[REG1]].4h, #0
351 ; CHECK-NEXT: ushll [[HI:v[0-9]+\.4s]], v0.4h, #0
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Dneon-shift-left-long.s25 ushll v0.8h, v1.8b, #3
26 ushll v0.4s, v1.4h, #3
27 ushll v0.2d, v1.2s, #3
Darm64-advsimd.s1602 ushll.8h v0, v0, #1
1604 ushll.4s v0, v0, #3
1606 ushll.2d v0, v0, #5
1774 ; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f]
1776 ; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f]
1778 ; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f]
1864 ushll v13.8h, v6.8b, #3
1865 ushll v14.4s, v7.4h, #2
1866 ushll v15.2d, v8.2s, #7
1926 ; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f]
[all …]
/external/llvm/test/MC/AArch64/
Dneon-shift-left-long.s25 ushll v0.8h, v1.8b, #3
26 ushll v0.4s, v1.4h, #3
27 ushll v0.2d, v1.2s, #3
Darm64-advsimd.s1602 ushll.8h v0, v0, #1
1604 ushll.4s v0, v0, #3
1606 ushll.2d v0, v0, #5
1774 ; CHECK: ushll.8h v0, v0, #1 ; encoding: [0x00,0xa4,0x09,0x2f]
1776 ; CHECK: ushll.4s v0, v0, #3 ; encoding: [0x00,0xa4,0x13,0x2f]
1778 ; CHECK: ushll.2d v0, v0, #5 ; encoding: [0x00,0xa4,0x25,0x2f]
1864 ushll v13.8h, v6.8b, #3
1865 ushll v14.4s, v7.4h, #2
1866 ushll v15.2d, v8.2s, #7
1926 ; CHECK: ushll.8h v13, v6, #3 ; encoding: [0xcd,0xa4,0x0b,0x2f]
[all …]
/external/capstone/suite/MC/AArch64/
Dneon-shift-left-long.s.cs8 0x20,0xa4,0x0b,0x2f = ushll v0.8h, v1.8b, #3
9 0x20,0xa4,0x13,0x2f = ushll v0.4s, v1.4h, #3
10 0x20,0xa4,0x23,0x2f = ushll v0.2d, v1.2s, #3

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