| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
| D | demand_shrink_nsw.ll | 4 ; %v43 getting removed so that %v44 is not illegally optimized away.
9 ; CHECK-NEXT: %v44 = or i32 %v43, -2147483648
10 ; CHECK-NEXT: %v45 = xor i32 %v44, 749011377
23 %v44 = or i32 %v43, -2147483648
24 %v45 = xor i32 %v44, 749011377
|
| /external/llvm/test/Transforms/InstCombine/ |
| D | demand_shrink_nsw.ll | 4 ; %v43 getting removed so that %v44 is not illegally optimized away.
9 ; CHECK-NEXT: %v44 = or i32 %v43, -2147483648
10 ; CHECK-NEXT: %v45 = xor i32 %v44, 749011377
23 %v44 = or i32 %v43, -2147483648
24 %v45 = xor i32 %v44, 749011377
|
| /external/deqp-deps/glslang/Test/baseResults/ |
| D | spv.swizzleInversion.frag.out | 17 Name 23 "v44"
48 23(v44): 22(ptr) Variable Function
61 Store 23(v44) 27
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | expand-condsets.ll | 39 %v16 = phi i32 [ 0, %b2 ], [ %v44, %b3 ]
67 %v44 = or i32 %v38, %v43
83 store i32 %v44, i32* %v52, align 4, !tbaa !0
87 %v53 = or i32 %v41, %v44
|
| D | upper-mpy.ll | 32 %v7 = phi i32* [ %v44, %b3 ], [ %a1, %b2 ]
72 %v44 = getelementptr inbounds i32, i32* %v7, i32 1
74 %v45 = icmp ult i32* %v44, %v40
|
| D | assert-postinc-ptr-not-value.ll | 77 %v44 = getelementptr inbounds %s.0, %s.0* %v34, i32 %v43, i32 0
78 %v45 = load i32, i32* %v44, align 4
80 store i32 %v46, i32* %v44, align 4
170 %v44 = load i32, i32* %v10, align 4
171 %v45 = lshr i32 %v44, 2
|
| D | reg_seq.ll | 60 %v44 = tail call i64 @llvm.hexagon.S2.vzxthw(i32 %v43)
63 %v47 = trunc i64 %v44 to i32
64 %v48 = lshr i64 %v44, 32
|
| D | v60-haar-postinc.ll | 69 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41)
71 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44)
72 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44)
|
| D | swp-disable-Os.ll | 58 %v44 = add i32 %v39, %v43
59 %v45 = add i32 %v40, %v44
63 %v49 = add i32 %v44, %v48
|
| D | swp-resmii-1.ll | 67 %v44 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v39, <16 x i32> %v41)
69 %v46 = tail call <16 x i32> @llvm.hexagon.V6.vavgh(<16 x i32> %v42, <16 x i32> %v44)
70 %v47 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v42, <16 x i32> %v44)
|
| D | vect-downscale.ll | 83 %v44 = phi <16 x i32>* [ %v54, %b5 ], [ %v43, %b4 ]
89 %v50 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 1
90 %v51 = load <16 x i32>, <16 x i32>* %v44, align 64, !tbaa !2
93 %v54 = getelementptr inbounds <16 x i32>, <16 x i32>* %v44, i32 2
|
| D | swp-bad-sched.ll | 79 %v44 = sub nsw i32 %v40, %v42
80 store i32 %v44, i32* %v41, align 4, !tbaa !0
83 %v47 = tail call i32 @llvm.hexagon.A2.abs(i32 %v44)
|
| D | constext-replace.ll | 126 %v44 = getelementptr inbounds [13595 x i32], [13595 x i32]* @g2, i32 0, i32 %v35
127 %v45 = load i32, i32* %v44, align 4
139 store i32 %v50, i32* %v44, align 4
|
| D | early-if-merge-loop.ll | 56 %v44 = shl nuw i64 %v43, 32
58 %v46 = or i64 %v44, %v45
|
| D | bug6757-endloop.ll | 101 %v44 = and i32 %v43, %v42
102 store volatile i32 %v44, i32* %v15, align 4
|
| D | bug-allocframe-size.ll | 89 %v44 = phi float [ %v43, %b9 ], [ %v42, %b8 ]
90 store float %v44, float* %v2, align 4, !tbaa !0
|
| D | swp-phi.ll | 58 %v44 = phi float [ undef, %b0 ], [ %v43, %b1 ]
59 %v45 = phi float [ undef, %b0 ], [ %v44, %b1 ]
93 %v79 = fmul float %v49, %v44
|
| D | registerscav-missing-spill-slot.ll | 123 %v44 = load double, double* null, align 8, !tbaa !0
124 %v45 = select i1 undef, double %v44, double %v36
129 %v50 = select i1 undef, double %v44, double %v37
|
| D | swp-phi-chains.ll | 52 %v11 = phi i32 [ %v4, %b0 ], [ %v44, %b1 ]
86 %v44 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v41, i32 %v43, i32 %v37)
87 store i32 %v44, i32* @g1, align 4
|
| D | vect-set_cc_v2i32.ll | 90 %v44 = phi i32 [ %v4, %b16 ], [ %v43, %b6 ]
91 %v45 = and i32 %v44, 2
110 %v58 = phi i32 [ %v44, %b7 ], [ %v57, %b8 ]
|
| D | v6-spill1.ll | 60 %v44 = tail call <512 x i1> @llvm.hexagon.V6.vgtub(<16 x i32> %v40, <16 x i32> %v1)
64 …%v48 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v44, <16 x i32> %v3, <16 x i32> %v36)
72 …%v56 = tail call <16 x i32> @llvm.hexagon.V6.vaddbnq(<512 x i1> %v44, <16 x i32> %v55, <16 x i32> …
198 %v7 = phi i32 [ 0, %b1 ], [ %v44, %b2 ]
236 %v44 = add nsw i32 %v7, 1
237 %v45 = icmp slt i32 %v44, %v1
|
| D | vect_setcc_v2i16.ll | 62 %v29 = phi i16* [ %v44, %b7 ], [ %v43, %b6 ]
80 %v44 = getelementptr [16 x i16], [16 x i16]* %v1, i32 0, i32 5
|
| D | bkfir.ll | 63 %v44 = icmp slt i32 %v43, %a4
64 br i1 %v44, label %b3, label %b4
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | float-cost.ll | 65 %v44 = uitofp i8 %v34 to float
69 %v48 = fsub float %v45, %v44
71 %v50 = fadd float %v49, %v44
|
| /external/deqp-deps/glslang/Test/ |
| D | spv.swizzleInversion.frag | 10 vec4 v44 = interpolateAtOffset(in4.zyxw, vec2(2.0));
|