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Searched refs:v_add_f16_e32 (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Dliteral16_vi.txt3 # VI: v_add_f16_e32 v1, 0.5, v3 ; encoding: [0xf0,0x06,0x02,0x3e]
6 # VI: v_add_f16_e32 v1, -0.5, v3 ; encoding: [0xf1,0x06,0x02,0x3e]
9 # VI: v_add_f16_e32 v1, 1.0, v3 ; encoding: [0xf2,0x06,0x02,0x3e]
12 # VI: v_add_f16_e32 v1, -1.0, v3 ; encoding: [0xf3,0x06,0x02,0x3e]
15 # VI: v_add_f16_e32 v1, 2.0, v3 ; encoding: [0xf4,0x06,0x02,0x3e]
18 # VI: v_add_f16_e32 v1, -2.0, v3 ; encoding: [0xf5,0x06,0x02,0x3e]
21 # VI: v_add_f16_e32 v1, 4.0, v3 ; encoding: [0xf6,0x06,0x02,0x3e]
24 # VI: v_add_f16_e32 v1, -4.0, v3 ; encoding: [0xf7,0x06,0x02,0x3e]
27 # VI: v_add_f16_e32 v1, 0.15915494, v3 ; encoding: [0xf8,0x06,0x02,0x3e]
30 # VI: v_add_f16_e32 v1, 0x41, v3 ; encoding: [0xff,0x06,0x02,0x3e,0x41,0x00,0x00,0x00]
[all …]
Dvop2_vi.txt195 # VI: v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]
Dgfx8_dasm_all.txt36378 # CHECK: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3e]
36381 # CHECK: v_add_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x3f]
36384 # CHECK: v_add_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3e]
36387 # CHECK: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3e]
36390 # CHECK: v_add_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x3e]
36393 # CHECK: v_add_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x3e]
36396 # CHECK: v_add_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x3e]
36399 # CHECK: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3e]
36402 # CHECK: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3e]
36405 # CHECK: v_add_f16_e32 v5, tba_lo, v2 ; encoding: [0x6c,0x04,0x0a,0x3e]
[all …]
Dgfx9_dasm_all.txt31164 # CHECK: v_add_f16_e32 v5, v1, v2 ; encoding: [0x01,0x05,0x0a,0x3e]
31167 # CHECK: v_add_f16_e32 v255, v1, v2 ; encoding: [0x01,0x05,0xfe,0x3f]
31170 # CHECK: v_add_f16_e32 v5, v255, v2 ; encoding: [0xff,0x05,0x0a,0x3e]
31173 # CHECK: v_add_f16_e32 v5, s1, v2 ; encoding: [0x01,0x04,0x0a,0x3e]
31176 # CHECK: v_add_f16_e32 v5, s101, v2 ; encoding: [0x65,0x04,0x0a,0x3e]
31179 # CHECK: v_add_f16_e32 v5, flat_scratch_lo, v2 ; encoding: [0x66,0x04,0x0a,0x3e]
31182 # CHECK: v_add_f16_e32 v5, flat_scratch_hi, v2 ; encoding: [0x67,0x04,0x0a,0x3e]
31185 # CHECK: v_add_f16_e32 v5, vcc_lo, v2 ; encoding: [0x6a,0x04,0x0a,0x3e]
31188 # CHECK: v_add_f16_e32 v5, vcc_hi, v2 ; encoding: [0x6b,0x04,0x0a,0x3e]
31191 # CHECK: v_add_f16_e32 v5, m0, v2 ; encoding: [0x7c,0x04,0x0a,0x3e]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dreduction.ll9 ; VI-NEXT: v_add_f16_e32
10 ; VI-NEXT: v_add_f16_e32
46 ; VI-NEXT: v_add_f16_e32
47 ; VI-NEXT: v_add_f16_e32
48 ; VI-NEXT: v_add_f16_e32
49 ; VI-NEXT: v_add_f16_e32
50 ; VI-NEXT: v_add_f16_e32
104 ; VI-NEXT: v_add_f16_e32
105 ; VI-NEXT: v_add_f16_e32
106 ; VI-NEXT: v_add_f16_e32
[all …]
Dfadd.f16.ll11 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], v[[A_F16]], v[[B_F16]]
31 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 1.0, v[[B_F16]]
49 ; VI: v_add_f16_e32 v[[R_F16:[0-9]+]], 2.0, v[[A_F16]]
82 ; VI-DAG: v_add_f16_e32 v[[R_F16_LO:[0-9]+]], v[[A_V2_F16]], v[[B_V2_F16]]
117 ; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], 1.0, v[[B_V2_F16]]
148 ; VI-DAG: v_add_f16_e32 v[[R_F16_1:[0-9]+]], 2.0, v[[A_V2_F16]]
Dfmuladd.f16.ll77 ; VI-DENORM-STRICT: v_add_f16_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
78 ; VI-DENORM-STRICT: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TMP]], [[R2]]
106 ; VI-DENORM-STRICT: v_add_f16_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
107 ; VI-DENORM-STRICT: v_add_f16_e32 [[RESULT:v[0-9]+]], [[R2]], [[TMP]]
352 ; VI-DENORM-STRICT: v_add_f16_e32 [[RESULT:v[0-9]+]], [[REGC]], [[TMP]]
414 ; VI-DENORM-STRICT: v_add_f16_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
442 ; VI-DENORM-STRICT: v_add_f16_e32 [[TMP:v[0-9]+]], [[R1]], [[R1]]
Domod.ll223 ; VI: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
234 ; VI: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
235 ; VI: v_add_f16_e32 v{{[0-9]+}}, [[ADD]], [[ADD]]{{$}}
Dfsub.f16.ll50 ; GFX89: v_add_f16_e32 v[[R_F16:[0-9]+]], -2.0, v[[A_F16]]
158 ; VI-DAG: v_add_f16_e32 v[[R_F16_0:[0-9]+]], -2.0, v[[A_V2_F16]]
Dcalling-conventions.ll28 ; VI: v_add_f16_e32 v0, 1.0, v0
Dimm16.ll218 ; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0.5, [[VAL]]
229 ; VI: v_add_f16_e32 [[REG:v[0-9]+]], 0x6400, [[VAL]]
Dllvm.round.ll73 ; GFX89: v_add_f16_e32 [[RESULT:v[0-9]+]], [[TRUNC]], [[SEL]]
Dfmed3.ll898 ; VI: v_add_f16_e32 v{{[0-9]+}}, 1.0
902 ; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0
931 ; GFX89-DAG: v_add_f16_e32 [[A_ADD:v[0-9]+]], 1.0, [[A]]
932 ; GFX89-DAG: v_add_f16_e32 [[B_ADD:v[0-9]+]], 2.0, [[B]]
933 ; GFX89-DAG: v_add_f16_e32 [[C_ADD:v[0-9]+]], 4.0, [[C]]
Dimmv216.ll317 ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, 0.5, v{{[0-9]+}}
336 ; VI-DAG: v_add_f16_e32 v{{[0-9]+}}, v{{[0-9]+}}, [[K]]
Dv_mac.ll258 ; VI-FLUSH: v_add_f16_e32 [[TMP2:v[0-9]+]], [[A]], [[A]]
Dclamp-modifier.ll332 ; GFX9: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}}
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dliteral16.s148 v_add_f16_e32 v1, 64.0, v2 label
Dvop2.s401 v_add_f16_e32 v1, v2, v3 label
/external/llvm/test/MC/Disassembler/AMDGPU/
Dvop2_vi.txt195 # VI: v_add_f16_e32 v1, v2, v3 ; encoding: [0x02,0x07,0x02,0x3e]