/external/llvm/test/MC/AMDGPU/ |
D | vop2-err.s | 44 v_addc_u32_e32 v1, vcc, v2, v3, s[2:3] label 47 v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3] label 50 v_addc_u32_e32 v1, vcc, v2, v3, -1 label 53 v_addc_u32_e32 v1, vcc, v2, v3, 123 label 56 v_addc_u32_e32 v1, vcc, v2, v3, s0 label 59 v_addc_u32_e32 v1, -1, v2, v3, s0 label
|
D | vop2.s | 327 v_addc_u32_e32 v1, vcc, v2, v3, vcc label
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/ |
D | vop2-err.s | 44 v_addc_u32_e32 v1, vcc, v2, v3, s[2:3] label 47 v_addc_u32_e32 v1, s[0:1], v2, v3, s[2:3] label 50 v_addc_u32_e32 v1, vcc, v2, v3, -1 label 53 v_addc_u32_e32 v1, vcc, v2, v3, 123 label 56 v_addc_u32_e32 v1, vcc, v2, v3, s0 label 59 v_addc_u32_e32 v1, -1, v2, v3, s0 label
|
D | vop2.s | 335 v_addc_u32_e32 v1, vcc, v2, v3, vcc label
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/ |
D | add_i128.ll | 5 ; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc 6 ; GCN-NEXT: v_addc_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc 7 ; GCN-NEXT: v_addc_u32_e32 v[[HI:[0-9]+]], vcc, v{{[0-9]+}}, v{{[0-9]+}}, vcc
|
D | store-hi16.ll | 108 ; GFX803-DAG: v_addc_u32_e32 132 ; GFX803-DAG: v_addc_u32_e32 155 ; GFX803-DAG: v_addc_u32_e32 179 ; GFX803-DAG: v_addc_u32_e32 297 ; GFX803-DAG: v_addc_u32_e32 316 ; GFX803: v_addc_u32_e32 342 ; GFX803-DAG: v_addc_u32_e32 364 ; GFX803-DAG: v_addc_u32_e32
|
D | split-scalar-i64-add.ll | 15 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 66 ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc
|
D | move-addr64-rsrc-dead-subreg-writes.ll | 19 ; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]]
|
D | uaddo.ll | 109 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 112 ; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc,
|
D | saddo.ll | 54 ; SICIVI: v_addc_u32_e32 v{{[0-9]+}}, vcc
|
D | add.ll | 174 ; GCN-NOT: v_addc_u32_e32 s
|
/external/llvm/test/CodeGen/AMDGPU/ |
D | split-scalar-i64-add.ll | 12 ; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc, 0, v{{[0-9]+}}, vcc 63 ; SI: v_addc_u32_e32 {{v[0-9]+}}, vcc, {{v[0-9]+}}, {{v[0-9]+}}, vcc
|
D | move-addr64-rsrc-dead-subreg-writes.ll | 19 ; GCN: v_addc_u32_e32 v[[PTRHI:[0-9]+]], vcc, v[[LDPTRHI]], v[[VARG1HI]]
|
D | add.ll | 145 ; SI-NOT: v_addc_u32_e32 s
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/Object/AMDGPU/ |
D | objdump.s | 42 v_addc_u32_e32 v11, vcc, v6, v11, vcc
|
/external/llvm/test/Object/AMDGPU/ |
D | objdump.s | 38 v_addc_u32_e32 v11, vcc, v6, v11, vcc
|
/external/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 138 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38] 141 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
|
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/ |
D | vop2_vi.txt | 138 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38] 141 # VI: v_addc_u32_e32 v1, vcc, v2, v3, vcc ; encoding: [0x02,0x07,0x02,0x38]
|
D | gfx8_dasm_all.txt | 36072 # CHECK: v_addc_u32_e32 v5, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0x0a,0x38] 36075 # CHECK: v_addc_u32_e32 v255, vcc, v1, v2, vcc ; encoding: [0x01,0x05,0xfe,0x39] 36078 # CHECK: v_addc_u32_e32 v5, vcc, v255, v2, vcc ; encoding: [0xff,0x05,0x0a,0x38] 36081 # CHECK: v_addc_u32_e32 v5, vcc, 0, v2, vcc ; encoding: [0x80,0x04,0x0a,0x38] 36084 # CHECK: v_addc_u32_e32 v5, vcc, -1, v2, vcc ; encoding: [0xc1,0x04,0x0a,0x38] 36087 # CHECK: v_addc_u32_e32 v5, vcc, 0.5, v2, vcc ; encoding: [0xf0,0x04,0x0a,0x38] 36090 # CHECK: v_addc_u32_e32 v5, vcc, -4.0, v2, vcc ; encoding: [0xf7,0x04,0x0a,0x38] 36093 # CHECK: v_addc_u32_e32 v5, vcc, v1, v255, vcc ; encoding: [0x01,0xff,0x0b,0x38]
|