Searched refs:v_mad_mixhi_f16 (Results 1 – 8 of 8) sorted by relevance
13 v_mad_mixhi_f16 v0, v1, v2, v3 label54 v_mad_mixhi_f16 v0, -v1, abs(v2), -abs(v3) label60 v_mad_mixhi_f16 v0, v1, v2, v3 clamp label102 v_mad_mixhi_f16 v0, v1, v2, v3 op_sel_hi:[1,0,1] clamp label
342 # GFX9: v_mad_mixhi_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]345 # GFX9: v_mad_mixhi_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]348 # GFX9: v_mad_mixhi_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]351 # GFX9: v_mad_mixhi_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]354 # GFX9: v_mad_mixhi_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]357 # GFX9: v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x66,0x04,0…360 # GFX9: v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x67,0x04,0…363 # GFX9: v_mad_mixhi_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]366 # GFX9: v_mad_mixhi_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]369 # GFX9: v_mad_mixhi_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04][all …]
50388 # CHECK: v_mad_mixhi_f16 v5, v1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]50391 # CHECK: v_mad_mixhi_f16 v255, v1, v2, v3 ; encoding: [0xff,0x00,0xa2,0xd3,0x01,0x05,0x0e,0x04]50394 # CHECK: v_mad_mixhi_f16 v5, v255, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0xff,0x05,0x0e,0x04]50397 # CHECK: v_mad_mixhi_f16 v5, s1, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x01,0x04,0x0e,0x04]50400 # CHECK: v_mad_mixhi_f16 v5, s101, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x65,0x04,0x0e,0x04]50403 # CHECK: v_mad_mixhi_f16 v5, flat_scratch_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x66,0x04,…50406 # CHECK: v_mad_mixhi_f16 v5, flat_scratch_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x67,0x04,…50409 # CHECK: v_mad_mixhi_f16 v5, vcc_lo, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6a,0x04,0x0e,0x04]50412 # CHECK: v_mad_mixhi_f16 v5, vcc_hi, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x6b,0x04,0x0e,0x04]50415 # CHECK: v_mad_mixhi_f16 v5, m0, v2, v3 ; encoding: [0x05,0x00,0xa2,0xd3,0x7c,0x04,0x0e,0x04][all …]
7 ; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v222 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v237 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v253 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v270 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2102 ; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}121 ; GFX9-NEXT: v_mad_mixhi_f16 v0, v0, v1, v2 op_sel_hi:[1,1,1] clamp{{$}}
83 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1]{{$}}99 ; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]100 ; GFX9-NEXT: v_mad_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]117 ; GFX9-NEXT: v_mad_mixhi_f16 v7, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1]118 ; GFX9-NEXT: v_mad_mixhi_f16 v6, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1]134 ; GFX9-NEXT: v_mad_mixhi_f16 v3, v0, v1, v2 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp{{$}}153 ; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp154 ; GFX9-NEXT: v_mad_mixhi_f16 v7, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp172 ; GFX9-NEXT: v_mad_mixhi_f16 v6, v0, v2, v4 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp174 ; GFX9-NEXT: v_mad_mixhi_f16 v2, v1, v3, v5 op_sel:[1,1,1] op_sel_hi:[1,1,1] clamp[all …]
144 def V_MAD_MIXHI_F16 : VOP3_VOP3PInst<"v_mad_mixhi_f16", VOP3_Profile<VOP_F16_F16_F16_F16, VOP3_OPSE…
93 "Has v_mad_mix_f32, v_mad_mixlo_f16, v_mad_mixhi_f16 instructions"
1550 …v_mad_mixhi_f16 dst, src0, src1, src2 :ref:`mad_mix_op_sel<amdgpu_synid_ma…