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Searched refs:val_0 (Results 1 – 6 of 6) sorted by relevance

/external/llvm/test/Transforms/MergeFunc/
Dno-merge-block-address-different-labels.ll22 ; Right here, this is val_0, and later the if might assign val_1
23 store i8* blockaddress(@_Z1fi, %val_0), i8** %l, align 8
37 val_0:
51 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
65 ; This time, we store val_1 initially, and later the if might assign val_0
73 store i8* blockaddress(@_Z1gi, %val_0), i8** %l, align 8
80 val_0:
94 indirectbr i8* %indirect.goto.dest, [label %val_1, label %val_0]
Dmerge-block-address.ll6 ; come from the same C-code, but in the first the two val_0/val_1 basic blocks
19 store i8* blockaddress(@_Z1fi, %val_0), i8** %l, align 8
37 val_0:
48 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
61 store i8* blockaddress(@_Z1gi, %val_0), i8** %l, align 8
75 val_0:
89 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/MergeFunc/
Dno-merge-block-address-different-labels.ll22 ; Right here, this is val_0, and later the if might assign val_1
23 store i8* blockaddress(@_Z1fi, %val_0), i8** %l, align 8
37 val_0:
51 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
65 ; This time, we store val_1 initially, and later the if might assign val_0
73 store i8* blockaddress(@_Z1gi, %val_0), i8** %l, align 8
80 val_0:
94 indirectbr i8* %indirect.goto.dest, [label %val_1, label %val_0]
Dmerge-block-address.ll6 ; come from the same C-code, but in the first the two val_0/val_1 basic blocks
19 store i8* blockaddress(@_Z1fi, %val_0), i8** %l, align 8
37 val_0:
48 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
61 store i8* blockaddress(@_Z1gi, %val_0), i8** %l, align 8
75 val_0:
89 indirectbr i8* %indirect.goto.dest, [label %val_0, label %val_1]
/external/tensorflow/tensorflow/python/data/kernel_tests/
Doptional_test.py72 val_0, val_1 = opt.get_value()
73 for expected, actual in [(st_0, val_0), (st_1, val_1)]:
/external/libhevc/common/arm/
Dihevc_resi_trans_neon_32x32.c1204 int16x4_t val_0 = vrshrn_n_s32(a[0], 15); in ihevc_resi_trans_32x32_neon() local
1206 vst1_lane_s16(pi2_dst, val_0, 0); /*Value 0*/ in ihevc_resi_trans_32x32_neon()
1207 vst1_lane_s16(pi2_dst + 8 * dst_strd, val_0, 2); /*Value 8*/ in ihevc_resi_trans_32x32_neon()
1208 vst1_lane_s16(pi2_dst + 16 * dst_strd, val_0, 1); /*Value 16*/ in ihevc_resi_trans_32x32_neon()
1209 vst1_lane_s16(pi2_dst + 24 * dst_strd, val_0, 3); /*Value 24*/ in ihevc_resi_trans_32x32_neon()