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Searched refs:val_cfg0 (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/arm/mach-imx/mx8m/
Dclock.c568 u32 val_cfg0, val_cfg1; in frac_pll_init() local
580 val_cfg0 = FRAC_PLL_CLKE_MASK | FRAC_PLL_REFCLK_SEL_OSC_25M | in frac_pll_init()
593 writel(val_cfg0 | FRAC_PLL_BYPASS_MASK, pll_cfg0); in frac_pll_init()
594 val_cfg0 = readl(pll_cfg0); in frac_pll_init()
597 ret = readl_poll_timeout(pll_cfg0, val_cfg0, in frac_pll_init()
598 val_cfg0 & FRAC_PLL_LOCK_MASK, 1); in frac_pll_init()
609 u32 val_cfg0, val_cfg1, val_cfg2, val; in sscg_pll_init() local
622 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
637 val_cfg0 = SSCG_PLL_CLKE_MASK | SSCG_PLL_DIV2_CLKE_MASK | in sscg_pll_init()
652 val_cfg0 = SSCG_PLL_PLL3_CLKE_MASK | SSCG_PLL_LOCK_SEL_MASK | in sscg_pll_init()
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