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/external/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s19 @ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3]
20 vcls.s8 d16, d16
21 @ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3]
22 vcls.s16 d16, d16
23 @ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3]
24 vcls.s32 d16, d16
25 @ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3]
26 vcls.s8 q8, q8
27 @ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3]
28 vcls.s16 q8, q8
[all …]
Dneont2-bitcount-encoding.s25 vcls.s8 d16, d16
26 vcls.s16 d16, d16
27 vcls.s32 d16, d16
28 vcls.s8 q8, q8
29 vcls.s16 q8, q8
30 vcls.s32 q8, q8
32 @ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s19 @ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3]
20 vcls.s8 d16, d16
21 @ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3]
22 vcls.s16 d16, d16
23 @ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3]
24 vcls.s32 d16, d16
25 @ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3]
26 vcls.s8 q8, q8
27 @ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3]
28 vcls.s16 q8, q8
[all …]
Dneont2-bitcount-encoding.s25 vcls.s8 d16, d16
26 vcls.s16 d16, d16
27 vcls.s32 d16, d16
28 vcls.s8 q8, q8
29 vcls.s16 q8, q8
30 vcls.s32 q8, q8
32 @ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-bitcount-encoding.s19 @ CHECK: vcls.s8 d16, d16 @ encoding: [0x20,0x04,0xf0,0xf3]
20 vcls.s8 d16, d16
21 @ CHECK: vcls.s16 d16, d16 @ encoding: [0x20,0x04,0xf4,0xf3]
22 vcls.s16 d16, d16
23 @ CHECK: vcls.s32 d16, d16 @ encoding: [0x20,0x04,0xf8,0xf3]
24 vcls.s32 d16, d16
25 @ CHECK: vcls.s8 q8, q8 @ encoding: [0x60,0x04,0xf0,0xf3]
26 vcls.s8 q8, q8
27 @ CHECK: vcls.s16 q8, q8 @ encoding: [0x60,0x04,0xf4,0xf3]
28 vcls.s16 q8, q8
[all …]
Dneont2-bitcount-encoding.s25 vcls.s8 d16, d16
26 vcls.s16 d16, d16
27 vcls.s32 d16, d16
28 vcls.s8 q8, q8
29 vcls.s16 q8, q8
30 vcls.s32 q8, q8
32 @ CHECK: vcls.s8 d16, d16 @ encoding: [0xf0,0xff,0x20,0x04]
33 @ CHECK: vcls.s16 d16, d16 @ encoding: [0xf4,0xff,0x20,0x04]
34 @ CHECK: vcls.s32 d16, d16 @ encoding: [0xf8,0xff,0x20,0x04]
35 @ CHECK: vcls.s8 q8, q8 @ encoding: [0xf0,0xff,0x60,0x04]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvcnt.ll80 ;CHECK: vcls.s8
82 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
88 ;CHECK: vcls.s16
90 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
96 ;CHECK: vcls.s32
98 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
104 ;CHECK: vcls.s8
106 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
112 ;CHECK: vcls.s16
114 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
[all …]
/external/capstone/suite/MC/ARM/
Dneon-bitcount-encoding.s.cs10 0x20,0x04,0xf0,0xf3 = vcls.s8 d16, d16
11 0x20,0x04,0xf4,0xf3 = vcls.s16 d16, d16
12 0x20,0x04,0xf8,0xf3 = vcls.s32 d16, d16
13 0x60,0x04,0xf0,0xf3 = vcls.s8 q8, q8
14 0x60,0x04,0xf4,0xf3 = vcls.s16 q8, q8
15 0x60,0x04,0xf8,0xf3 = vcls.s32 q8, q8
Dneont2-bitcount-encoding.s.cs10 0xf0,0xff,0x20,0x04 = vcls.s8 d16, d16
11 0xf4,0xff,0x20,0x04 = vcls.s16 d16, d16
12 0xf8,0xff,0x20,0x04 = vcls.s32 d16, d16
13 0xf0,0xff,0x60,0x04 = vcls.s8 q8, q8
14 0xf4,0xff,0x60,0x04 = vcls.s16 q8, q8
15 0xf8,0xff,0x60,0x04 = vcls.s32 q8, q8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
159 ;CHECK: vcls.s8
161 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
167 ;CHECK: vcls.s16
169 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
175 ;CHECK: vcls.s32
177 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
183 ;CHECK: vcls.s8
185 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
191 ;CHECK: vcls.s16
[all …]
Dpopcnt.ll155 ;CHECK: vcls.s8
157 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
163 ;CHECK: vcls.s16
165 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
171 ;CHECK: vcls.s32
173 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
179 ;CHECK: vcls.s8
181 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
187 ;CHECK: vcls.s16
189 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
[all …]
/external/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
159 ;CHECK: vcls.s8
161 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
167 ;CHECK: vcls.s16
169 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
175 ;CHECK: vcls.s32
177 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
183 ;CHECK: vcls.s8
185 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
191 ;CHECK: vcls.s16
[all …]
Dpopcnt.ll155 ;CHECK: vcls.s8
157 %tmp2 = call <8 x i8> @llvm.arm.neon.vcls.v8i8(<8 x i8> %tmp1)
163 ;CHECK: vcls.s16
165 %tmp2 = call <4 x i16> @llvm.arm.neon.vcls.v4i16(<4 x i16> %tmp1)
171 ;CHECK: vcls.s32
173 %tmp2 = call <2 x i32> @llvm.arm.neon.vcls.v2i32(<2 x i32> %tmp1)
179 ;CHECK: vcls.s8
181 %tmp2 = call <16 x i8> @llvm.arm.neon.vcls.v16i8(<16 x i8> %tmp1)
187 ;CHECK: vcls.s16
189 %tmp2 = call <8 x i16> @llvm.arm.neon.vcls.v8i16(<8 x i16> %tmp1)
[all …]
/external/arm-neon-tests/
Dref_vcls.c34 #define INSN_NAME vcls
DMakefile.gcc59 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt265 # CHECK: vcls.s8 d16, d16
267 # CHECK: vcls.s16 d16, d16
269 # CHECK: vcls.s32 d16, d16
271 # CHECK: vcls.s8 q8, q8
273 # CHECK: vcls.s16 q8, q8
275 # CHECK: vcls.s32 q8, q8
Dneon.txt269 # CHECK: vcls.s8 d16, d16
271 # CHECK: vcls.s16 d16, d16
273 # CHECK: vcls.s32 d16, d16
275 # CHECK: vcls.s8 q8, q8
277 # CHECK: vcls.s16 q8, q8
279 # CHECK: vcls.s32 q8, q8
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneont2.txt265 # CHECK: vcls.s8 d16, d16
267 # CHECK: vcls.s16 d16, d16
269 # CHECK: vcls.s32 d16, d16
271 # CHECK: vcls.s8 q8, q8
273 # CHECK: vcls.s16 q8, q8
275 # CHECK: vcls.s32 q8, q8
Dneon.txt269 # CHECK: vcls.s8 d16, d16
271 # CHECK: vcls.s16 d16, d16
273 # CHECK: vcls.s32 d16, d16
275 # CHECK: vcls.s8 q8, q8
277 # CHECK: vcls.s16 q8, q8
279 # CHECK: vcls.s32 q8, q8
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt265 # CHECK: vcls.s8 d16, d16
267 # CHECK: vcls.s16 d16, d16
269 # CHECK: vcls.s32 d16, d16
271 # CHECK: vcls.s8 q8, q8
273 # CHECK: vcls.s16 q8, q8
275 # CHECK: vcls.s32 q8, q8
Dneon.txt269 # CHECK: vcls.s8 d16, d16
271 # CHECK: vcls.s16 d16, d16
273 # CHECK: vcls.s32 d16, d16
275 # CHECK: vcls.s8 q8, q8
277 # CHECK: vcls.s16 q8, q8
279 # CHECK: vcls.s32 q8, q8
/external/vixl/src/aarch32/
Dassembler-aarch32.h4146 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
4147 void vcls(DataType dt, DRegister rd, DRegister rm) { vcls(al, dt, rd, rm); } in vcls() function
4149 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
4150 void vcls(DataType dt, QRegister rd, QRegister rm) { vcls(al, dt, rd, rm); } in vcls() function
Ddisasm-aarch32.h1628 void vcls(Condition cond, DataType dt, DRegister rd, DRegister rm);
1630 void vcls(Condition cond, DataType dt, QRegister rd, QRegister rm);
/external/clang/include/clang/Basic/
Darm_neon.td793 def VCLS : SInst<"vcls", "dd", "csiQcQsQi">;

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