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Searched refs:vclt (Results 1 – 25 of 41) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-cmp-encoding.s107 vclt.s8 d16, d16, #0
113 @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
116 vclt.s8 q12, q13, q3
117 vclt.s16 q12, q13, q3
118 vclt.s32 q12, q13, q3
119 vclt.u8 q12, q13, q3
120 vclt.u16 q12, q13, q3
121 vclt.u32 q12, q13, q3
122 vclt.f32 q12, q13, q3
124 vclt.s8 d12, d13, d3
[all …]
Dfullfp16-neon.s130 vclt.f16 d2, d3, d4
131 vclt.f16 q2, q3, q4
137 vclt.f16 d2, d3, #0
138 vclt.f16 q2, q3, #0
139 @ ARM: vclt.f16 d2, d3, #0 @ encoding: [0x03,0x26,0xb5,0xf3]
140 @ ARM: vclt.f16 q2, q3, #0 @ encoding: [0x46,0x46,0xb5,0xf3]
141 @ THUMB: vclt.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x26]
142 @ THUMB: vclt.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x46]
Dfullfp16-neon-neg.s96 vclt.f16 d2, d3, d4
97 vclt.f16 q2, q3, q4
101 vclt.f16 d2, d3, #0
102 vclt.f16 q2, q3, #0
Dneon-bitwise-encoding.s304 vclt.s16 q5, #0
305 vclt.s16 d5, #0
/external/llvm/test/MC/ARM/
Dneon-cmp-encoding.s107 vclt.s8 d16, d16, #0
113 @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
116 vclt.s8 q12, q13, q3
117 vclt.s16 q12, q13, q3
118 vclt.s32 q12, q13, q3
119 vclt.u8 q12, q13, q3
120 vclt.u16 q12, q13, q3
121 vclt.u32 q12, q13, q3
122 vclt.f32 q12, q13, q3
124 vclt.s8 d12, d13, d3
[all …]
Dfullfp16-neon.s130 vclt.f16 d2, d3, d4
131 vclt.f16 q2, q3, q4
137 vclt.f16 d2, d3, #0
138 vclt.f16 q2, q3, #0
139 @ ARM: vclt.f16 d2, d3, #0 @ encoding: [0x03,0x26,0xb5,0xf3]
140 @ ARM: vclt.f16 q2, q3, #0 @ encoding: [0x46,0x46,0xb5,0xf3]
141 @ THUMB: vclt.f16 d2, d3, #0 @ encoding: [0xb5,0xff,0x03,0x26]
142 @ THUMB: vclt.f16 q2, q3, #0 @ encoding: [0xb5,0xff,0x46,0x46]
Dfullfp16-neon-neg.s96 vclt.f16 d2, d3, d4
97 vclt.f16 q2, q3, q4
101 vclt.f16 d2, d3, #0
102 vclt.f16 q2, q3, #0
Dneon-bitwise-encoding.s304 vclt.s16 q5, #0
305 vclt.s16 d5, #0
/external/libavc/common/arm/
Dih264_deblk_chroma_a9.s193 vclt.u8 q4, q4, q11 @|p0-q0| < alpha ?
194 vclt.u8 q5, q5, q12 @|q1-q0| < beta ?
195 vclt.u8 q6, q6, q12 @|p1-p0| < beta ?
395 vclt.u8 q4, q4, q11 @|p0-q0| < alpha ?
397 vclt.u8 q5, q5, q12 @|q1-q0| < beta ?
399 vclt.u8 q6, q6, q12 @|p1-p0| < beta ?
522 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
523 vclt.u8 d5, d5, d12 @|q1-q0| < beta ?
524 vclt.u8 d6, d6, d12 @|p1-p0| < beta ?
606 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
[all …]
Dih264_resi_trans_quant_a9.s192 vclt.s16 q2, q12, #0 @Get the sign of row 1 blk 1
195 vclt.s16 q3, q13, #0 @Get the sign of row 2 blk 1
387 vclt.s16 q2, q12, #0 @Get the sign of row 1 blk 1
390 vclt.s16 q3, q13, #0 @Get the sign of row 2 blk 1
531 vclt.s16 q3, q0, #0 @get the sign row 1,2
532 vclt.s16 q4, q1, #0
648 vclt.s32 q4, q0, #0 @get the sign row 1,2
650 vclt.s32 q5, q1, #0
Dih264_deblk_luma_a9.s258 vclt.u8 q11, q11, q1 @Aq < Beta
259 vclt.u8 q10, q6, q10 @(ABS(p0 - q0) <((Alpha >>2) + 2))
/external/arm-neon-tests/
Dref_vclt.c26 #define INSN_NAME vclt
DMakefile.gcc47 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
DMakefile41 vcgt vclt vbsl vshl vldX vdup_lane vrshrn_n vqdmull_lane \
/external/capstone/suite/MC/ARM/
Dneon-bitwise-encoding.s.cs107 0x4a,0xa2,0xb5,0xf3 = vclt.s16 q5, q5, #0
108 0x05,0x52,0xb5,0xf3 = vclt.s16 d5, d5, #0
Dneon-cmp-encoding.s.cs52 0x20,0x02,0xf1,0xf3 = vclt.s8 d16, d16, #0
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-cmp-encoding.s107 vclt.s8 d16, d16, #0
113 @ CHECK: vclt.s8 d16, d16, #0 @ encoding: [0x20,0x02,0xf1,0xf3]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
Dfullfp16-neon-arm.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
/external/llvm/test/MC/Disassembler/ARM/
Dfullfp16-neon-thumb.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
Dfullfp16-neon-arm.txt89 # CHECK: vclt.f16 d2, d3, #0
90 # CHECK: vclt.f16 q2, q3, #0
/external/libmpeg2/common/arm/
Dideint_cac_a9.s208 vclt.u32 d0, d21, d20
/external/vixl/test/aarch32/
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-a32.cc58 M(vclt) \
Dtest-assembler-cond-dt-drt-drd-drn-drm-float-f32-only-t32.cc58 M(vclt) \
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvcgt.ll193 ;CHECK: vclt.s8

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