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Searched refs:vclz (Results 1 – 25 of 43) sorted by relevance

12

/external/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz.i16 q8, q8
[all …]
Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz.i16 q8, q8
[all …]
Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-bitcount-encoding.s7 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xa0,0x04,0xf0,0xf3]
8 vclz.i8 d16, d16
9 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xa0,0x04,0xf4,0xf3]
10 vclz.i16 d16, d16
11 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xa0,0x04,0xf8,0xf3]
12 vclz.i32 d16, d16
13 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xe0,0x04,0xf0,0xf3]
14 vclz.i8 q8, q8
15 @ CHECK: vclz.i16 q8, q8 @ encoding: [0xe0,0x04,0xf4,0xf3]
16 vclz.i16 q8, q8
[all …]
Dneont2-bitcount-encoding.s11 vclz.i8 d16, d16
12 vclz.i16 d16, d16
13 vclz.i32 d16, d16
14 vclz.i8 q8, q8
15 vclz.i16 q8, q8
16 vclz.i32 q8, q8
18 @ CHECK: vclz.i8 d16, d16 @ encoding: [0xf0,0xff,0xa0,0x04]
19 @ CHECK: vclz.i16 d16, d16 @ encoding: [0xf4,0xff,0xa0,0x04]
20 @ CHECK: vclz.i32 d16, d16 @ encoding: [0xf8,0xff,0xa0,0x04]
21 @ CHECK: vclz.i8 q8, q8 @ encoding: [0xf0,0xff,0xe0,0x04]
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvcnt.ll24 ;CHECK: vclz.i8
26 %tmp2 = call <8 x i8> @llvm.arm.neon.vclz.v8i8(<8 x i8> %tmp1)
32 ;CHECK: vclz.i16
34 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
40 ;CHECK: vclz.i32
42 %tmp2 = call <2 x i32> @llvm.arm.neon.vclz.v2i32(<2 x i32> %tmp1)
48 ;CHECK: vclz.i8
50 %tmp2 = call <16 x i8> @llvm.arm.neon.vclz.v16i8(<16 x i8> %tmp1)
56 ;CHECK: vclz.i16
58 %tmp2 = call <8 x i16> @llvm.arm.neon.vclz.v8i16(<8 x i16> %tmp1)
[all …]
/external/capstone/suite/MC/ARM/
Dneon-bitcount-encoding.s.cs4 0xa0,0x04,0xf0,0xf3 = vclz.i8 d16, d16
5 0xa0,0x04,0xf4,0xf3 = vclz.i16 d16, d16
6 0xa0,0x04,0xf8,0xf3 = vclz.i32 d16, d16
7 0xe0,0x04,0xf0,0xf3 = vclz.i8 q8, q8
8 0xe0,0x04,0xf4,0xf3 = vclz.i16 q8, q8
9 0xe0,0x04,0xf8,0xf3 = vclz.i32 q8, q8
Dneont2-bitcount-encoding.s.cs4 0xf0,0xff,0xa0,0x04 = vclz.i8 d16, d16
5 0xf4,0xff,0xa0,0x04 = vclz.i16 d16, d16
6 0xf8,0xff,0xa0,0x04 = vclz.i32 d16, d16
7 0xf0,0xff,0xe0,0x04 = vclz.i8 q8, q8
8 0xf4,0xff,0xe0,0x04 = vclz.i16 q8, q8
9 0xf8,0xff,0xe0,0x04 = vclz.i32 q8, q8
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
25 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
33 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
41 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
56 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
64 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
72 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
87 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
95 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
103 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
[all …]
Dpopcnt.ll99 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
107 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
115 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
123 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
131 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
139 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
Dcttz_vector.ll285 ; CHECK: vclz.i16 [[D1]], [[D1]]
300 ; CHECK: vclz.i16 [[Q1]], [[Q1]]
323 ; CHECK: vclz.i32 [[D1]], [[D1]]
338 ; CHECK: vclz.i32 [[Q1]], [[Q1]]
/external/llvm/test/CodeGen/ARM/
Dvcnt.ll2 ; NB: this tests vcnt, vclz, and vcls
25 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
33 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
41 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
56 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
64 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
72 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
87 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
95 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
103 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
[all …]
Dpopcnt.ll99 ;CHECK: vclz.i8 {{d[0-9]+}}, {{d[0-9]+}}
107 ;CHECK: vclz.i16 {{d[0-9]+}}, {{d[0-9]+}}
115 ;CHECK: vclz.i32 {{d[0-9]+}}, {{d[0-9]+}}
123 ;CHECK: vclz.i8 {{q[0-9]+}}, {{q[0-9]+}}
131 ;CHECK: vclz.i16 {{q[0-9]+}}, {{q[0-9]+}}
139 ;CHECK: vclz.i32 {{q[0-9]+}}, {{q[0-9]+}}
Dcttz_vector.ll285 ; CHECK: vclz.i16 [[D1]], [[D1]]
300 ; CHECK: vclz.i16 [[Q1]], [[Q1]]
323 ; CHECK: vclz.i32 [[D1]], [[D1]]
338 ; CHECK: vclz.i32 [[Q1]], [[Q1]]
/external/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll7 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
8 ret <8 x i8> %vclz.i
15 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
16 ret <8 x i8> %vclz.i
67 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
68 ret <16 x i8> %vclz.i
75 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
76 ret <16 x i8> %vclz.i
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vclz.ll7 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
8 ret <8 x i8> %vclz.i
15 %vclz.i = tail call <8 x i8> @llvm.ctlz.v8i8(<8 x i8> %a, i1 false) nounwind
16 ret <8 x i8> %vclz.i
67 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
68 ret <16 x i8> %vclz.i
75 %vclz.i = tail call <16 x i8> @llvm.ctlz.v16i8(<16 x i8> %a, i1 false) nounwind
76 ret <16 x i8> %vclz.i
/external/llvm/test/Bitcode/
Darm32_neon_vcnt_upgrade.ll3 ; Tests vclz and vcnt
8 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
21 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/
Darm32_neon_vcnt_upgrade.ll3 ; Tests vclz and vcnt
8 %tmp2 = call <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16> %tmp1)
21 declare <4 x i16> @llvm.arm.neon.vclz.v4i16(<4 x i16>) nounwind readnone
/external/arm-neon-tests/
DMakefile.gcc59 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
DMakefile53 vqshlu_n vclz vcls vcnt vqshrn_n vpmax vpmin vqshrun_n \
Dref_vclz.c34 #define INSN_NAME vclz
/external/libjpeg-turbo/simd/arm/
Djsimd_neon.S2595 vclz.i16 q0, q0
2596 vclz.i16 q1, q1
2597 vclz.i16 q2, q2
2598 vclz.i16 q3, q3
2703 vclz.i16 q4, q4
2704 vclz.i16 q5, q5
2705 vclz.i16 q6, q6
2706 vclz.i16 q7, q7
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt253 # CHECK: vclz.i8 d16, d16
255 # CHECK: vclz.i16 d16, d16
257 # CHECK: vclz.i32 d16, d16
259 # CHECK: vclz.i8 q8, q8
261 # CHECK: vclz.i16 q8, q8
263 # CHECK: vclz.i32 q8, q8
Dneon.txt257 # CHECK: vclz.i8 d16, d16
259 # CHECK: vclz.i16 d16, d16
261 # CHECK: vclz.i32 d16, d16
263 # CHECK: vclz.i8 q8, q8
265 # CHECK: vclz.i16 q8, q8
267 # CHECK: vclz.i32 q8, q8

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