| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | fpvcvtr.ll | 4 declare float @llvm.arm.vcvtr.f32(float)
6 declare float @llvm.arm.vcvtr.f64(double)
11 ; CHECK-VFP: vcvtr.s32.f32 s0, s0
12 %vcvtr = tail call float @llvm.arm.vcvtr.f32(float %f)
13 ret float %vcvtr
18 ; CHECK-VFP: vcvtr.u32.f32 s0, s0
19 %vcvtr = tail call float @llvm.arm.vcvtru.f32(float %f)
20 ret float %vcvtr
25 ; CHECK-VFP: vcvtr.s32.f64 s0, d{{.*}}
26 %vcvtr = tail call float @llvm.arm.vcvtr.f64(double %d)
[all …]
|
| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | simple-fp-encoding.s | 235 @ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
236 @ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
237 @ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
238 @ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee]
239 vcvtr.s32.f64 s0, d0
240 vcvtr.s32.f32 s0, s1
241 vcvtr.u32.f64 s0, d0
242 vcvtr.u32.f32 s0, s1
|
| /external/capstone/suite/MC/ARM/ |
| D | simple-fp-encoding.s.cs | 124 0x40,0x0b,0xbd,0xee = vcvtr.s32.f64 s0, d0
125 0x60,0x0a,0xbd,0xee = vcvtr.s32.f32 s0, s1
126 0x40,0x0b,0xbc,0xee = vcvtr.u32.f64 s0, d0
127 0x60,0x0a,0xbc,0xee = vcvtr.u32.f32 s0, s1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 326 @ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
327 @ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
328 @ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
329 @ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee]
330 vcvtr.s32.f64 s0, d0
331 vcvtr.s32.f32 s0, s1
332 vcvtr.u32.f64 s0, d0
333 vcvtr.u32.f32 s0, s1
|
| D | fullfp16.s | 81 vcvtr.s32.f16 s0, s1
82 vcvtr.u32.f16 s0, s1
83 @ ARM: vcvtr.s32.f16 s0, s1 @ encoding: [0x60,0x09,0xbd,0xee]
84 @ ARM: vcvtr.u32.f16 s0, s1 @ encoding: [0x60,0x09,0xbc,0xee]
85 @ THUMB: vcvtr.s32.f16 s0, s1 @ encoding: [0xbd,0xee,0x60,0x09]
86 @ THUMB: vcvtr.u32.f16 s0, s1 @ encoding: [0xbc,0xee,0x60,0x09]
|
| D | single-precision-fp.s | 82 vcvtr.s32.f64 s1, d0
83 vcvtr.u32.f64 s1, d2
101 @ CHECK-ERRORS-NEXT: vcvtr.s32.f64 s1, d0
103 @ CHECK-ERRORS-NEXT: vcvtr.u32.f64 s1, d2
|
| D | fullfp16-neg.s | 61 vcvtr.s32.f16 s0, s1
62 vcvtr.u32.f16 s0, s1
|
| /external/llvm/test/MC/ARM/ |
| D | simple-fp-encoding.s | 314 @ CHECK: vcvtr.s32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbd,0xee]
315 @ CHECK: vcvtr.s32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbd,0xee]
316 @ CHECK: vcvtr.u32.f64 s0, d0 @ encoding: [0x40,0x0b,0xbc,0xee]
317 @ CHECK: vcvtr.u32.f32 s0, s1 @ encoding: [0x60,0x0a,0xbc,0xee]
318 vcvtr.s32.f64 s0, d0
319 vcvtr.s32.f32 s0, s1
320 vcvtr.u32.f64 s0, d0
321 vcvtr.u32.f32 s0, s1
|
| D | fullfp16.s | 81 vcvtr.s32.f16 s0, s1
82 vcvtr.u32.f16 s0, s1
83 @ ARM: vcvtr.s32.f16 s0, s1 @ encoding: [0x60,0x09,0xbd,0xee]
84 @ ARM: vcvtr.u32.f16 s0, s1 @ encoding: [0x60,0x09,0xbc,0xee]
85 @ THUMB: vcvtr.s32.f16 s0, s1 @ encoding: [0xbd,0xee,0x60,0x09]
86 @ THUMB: vcvtr.u32.f16 s0, s1 @ encoding: [0xbc,0xee,0x60,0x09]
|
| D | single-precision-fp.s | 82 vcvtr.s32.f64 s1, d0
83 vcvtr.u32.f64 s1, d2
101 @ CHECK-ERRORS-NEXT: vcvtr.s32.f64 s1, d0
103 @ CHECK-ERRORS-NEXT: vcvtr.u32.f64 s1, d2
|
| D | fullfp16-neg.s | 61 vcvtr.s32.f16 s0, s1
62 vcvtr.u32.f16 s0, s1
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 210 # CHECK: vcvtr.s32.f64 s0, d0
211 # CHECK: vcvtr.s32.f32 s0, s1
212 # CHECK: vcvtr.u32.f64 s0, d0
213 # CHECK: vcvtr.u32.f32 s0, s1
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 259 # CHECK: vcvtr.s32.f64 s0, d0
260 # CHECK: vcvtr.s32.f32 s0, s1
261 # CHECK: vcvtr.u32.f64 s0, d0
262 # CHECK: vcvtr.u32.f32 s0, s1
|
| D | fullfp16-thumb.txt | 60 # CHECK: vcvtr.s32.f16 s0, s1
61 # CHECK: vcvtr.u32.f16 s0, s1
|
| D | fullfp16-arm.txt | 60 # CHECK: vcvtr.s32.f16 s0, s1
61 # CHECK: vcvtr.u32.f16 s0, s1
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | fp-encoding.txt | 259 # CHECK: vcvtr.s32.f64 s0, d0
260 # CHECK: vcvtr.s32.f32 s0, s1
261 # CHECK: vcvtr.u32.f64 s0, d0
262 # CHECK: vcvtr.u32.f32 s0, s1
|
| D | fullfp16-arm.txt | 60 # CHECK: vcvtr.s32.f16 s0, s1
61 # CHECK: vcvtr.u32.f16 s0, s1
|
| D | fullfp16-thumb.txt | 60 # CHECK: vcvtr.s32.f16 s0, s1
61 # CHECK: vcvtr.u32.f16 s0, s1
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1475 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1482 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1489 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1496 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1503 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1510 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
2222 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
2224 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
2226 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
2228 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 1551 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
1559 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
1567 IIC_fpCVTHI, "vcvtr", ".s32.f16\t$Sd, $Sm",
1575 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
1583 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
1591 IIC_fpCVTHI, "vcvtr", ".u32.f16\t$Sd, $Sm",
2396 def : VFP2MnemonicAlias<"ftosid", "vcvtr.s32.f64">;
2398 def : VFP2MnemonicAlias<"ftosis", "vcvtr.s32.f32">;
2400 def : VFP2MnemonicAlias<"ftouid", "vcvtr.u32.f64">;
2402 def : VFP2MnemonicAlias<"ftouis", "vcvtr.u32.f32">;
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrVFP.td | 759 IIC_fpCVTDI, "vcvtr", ".s32.f64\t$Sd, $Dm",
766 IIC_fpCVTSI, "vcvtr", ".s32.f32\t$Sd, $Sm",
773 IIC_fpCVTDI, "vcvtr", ".u32.f64\t$Sd, $Dm",
780 IIC_fpCVTSI, "vcvtr", ".u32.f32\t$Sd, $Sm",
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 4345 void vcvtr(
4347 void vcvtr(DataType dt1, DataType dt2, SRegister rd, SRegister rm) { in vcvtr() function
4348 vcvtr(al, dt1, dt2, rd, rm); in vcvtr()
4351 void vcvtr(
4353 void vcvtr(DataType dt1, DataType dt2, SRegister rd, DRegister rm) { in vcvtr() function
4354 vcvtr(al, dt1, dt2, rd, rm); in vcvtr()
|
| D | disasm-aarch32.h | 1755 void vcvtr(
1758 void vcvtr(
|
| D | disasm-aarch32.cc | 4640 void Disassembler::vcvtr( in vcvtr() function in vixl::aarch32::Disassembler
4647 void Disassembler::vcvtr( in vcvtr() function in vixl::aarch32::Disassembler
23897 vcvtr(CurrentCond(), in DecodeT32()
23921 vcvtr(CurrentCond(), in DecodeT32()
24243 vcvtr(CurrentCond(), in DecodeT32()
24267 vcvtr(CurrentCond(), in DecodeT32()
66547 vcvtr(condition, in DecodeA32()
66581 vcvtr(condition, in DecodeA32()
66995 vcvtr(condition, in DecodeA32()
67029 vcvtr(condition, in DecodeA32()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1177 Mnemonic = "vcvtr.s32.f64";
1181 Mnemonic = "vcvtr.s32.f32";
1192 Mnemonic = "vcvtr.u32.f64";
1196 Mnemonic = "vcvtr.u32.f32";
7774 "vcvtm\005vcvtn\005vcvtp\005vcvtr\005vcvtt\004vdiv\004vdup\004veor\004ve"
9744 …{ 1947 /* vcvtr */, ARM::VTOSIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_Con…
9745 …{ 1947 /* vcvtr */, ARM::VTOSIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_Ha…
9746 …{ 1947 /* vcvtr */, ARM::VTOSIRH, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasFullFP16, { MCK…
9747 …{ 1947 /* vcvtr */, ARM::VTOUIRS, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2, { MCK_Con…
9748 …{ 1947 /* vcvtr */, ARM::VTOUIRD, Convert__Reg1_3__Reg1_4__CondCode2_0, Feature_HasVFP2|Feature_Ha…
[all …]
|