Home
last modified time | relevance | path

Searched refs:vhsub (Results 1 – 24 of 24) sorted by relevance

/external/llvm/test/MC/ARM/
Dneon-sub-encoding.s73 @ CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2]
74 vhsub.s8 d16, d16, d17
75 @ CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2]
76 vhsub.s16 d16, d16, d17
77 @ CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2]
78 vhsub.s32 d16, d16, d17
79 @ CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3]
80 vhsub.u8 d16, d16, d17
81 @ CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3]
82 vhsub.u16 d16, d16, d17
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-sub-encoding.s73 @ CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2]
74 vhsub.s8 d16, d16, d17
75 @ CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2]
76 vhsub.s16 d16, d16, d17
77 @ CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2]
78 vhsub.s32 d16, d16, d17
79 @ CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3]
80 vhsub.u8 d16, d16, d17
81 @ CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3]
82 vhsub.u16 d16, d16, d17
[all …]
/external/capstone/suite/MC/ARM/
Dneon-sub-encoding.s.cs34 0xa1,0x02,0x40,0xf2 = vhsub.s8 d16, d16, d17
35 0xa1,0x02,0x50,0xf2 = vhsub.s16 d16, d16, d17
36 0xa1,0x02,0x60,0xf2 = vhsub.s32 d16, d16, d17
37 0xa1,0x02,0x40,0xf3 = vhsub.u8 d16, d16, d17
38 0xa1,0x02,0x50,0xf3 = vhsub.u16 d16, d16, d17
39 0xa1,0x02,0x60,0xf3 = vhsub.u32 d16, d16, d17
40 0xe2,0x02,0x40,0xf2 = vhsub.s8 q8, q8, q9
41 0xe2,0x02,0x50,0xf2 = vhsub.s16 q8, q8, q9
42 0xe2,0x02,0x60,0xf2 = vhsub.s32 q8, q8, q9
65 0x28,0xb2,0x0b,0xf2 = vhsub.s8 d11, d11, d24
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-sub-encoding.s47 @ CHECK: vhsub.s8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf2]
48 vhsub.s8 d16, d16, d17
49 @ CHECK: vhsub.s16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf2]
50 vhsub.s16 d16, d16, d17
51 @ CHECK: vhsub.s32 d16, d16, d17 @ encoding: [0xa1,0x02,0x60,0xf2]
52 vhsub.s32 d16, d16, d17
53 @ CHECK: vhsub.u8 d16, d16, d17 @ encoding: [0xa1,0x02,0x40,0xf3]
54 vhsub.u8 d16, d16, d17
55 @ CHECK: vhsub.u16 d16, d16, d17 @ encoding: [0xa1,0x02,0x50,0xf3]
56 vhsub.u16 d16, d16, d17
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvhsub.ll5 ;CHECK: vhsub.s8
14 ;CHECK: vhsub.s16
23 ;CHECK: vhsub.s32
32 ;CHECK: vhsub.u8
41 ;CHECK: vhsub.u16
50 ;CHECK: vhsub.u32
59 ;CHECK: vhsub.s8
68 ;CHECK: vhsub.s16
77 ;CHECK: vhsub.s32
86 ;CHECK: vhsub.u8
[all …]
/external/llvm/test/CodeGen/ARM/
Dvhsub.ll5 ;CHECK: vhsub.s8
14 ;CHECK: vhsub.s16
23 ;CHECK: vhsub.s32
32 ;CHECK: vhsub.u8
41 ;CHECK: vhsub.u16
50 ;CHECK: vhsub.u32
59 ;CHECK: vhsub.s8
68 ;CHECK: vhsub.s16
77 ;CHECK: vhsub.s32
86 ;CHECK: vhsub.u8
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvhsub.ll5 ;CHECK: vhsub.s8
14 ;CHECK: vhsub.s16
23 ;CHECK: vhsub.s32
32 ;CHECK: vhsub.u8
41 ;CHECK: vhsub.u16
50 ;CHECK: vhsub.u32
59 ;CHECK: vhsub.s8
68 ;CHECK: vhsub.s16
77 ;CHECK: vhsub.s32
86 ;CHECK: vhsub.u8
[all …]
/external/arm-neon-tests/
Dref_vhsub.c26 #define INSN_NAME vhsub
DMakefile.gcc57 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
DMakefile51 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
/external/libhevc/common/arm/
Dihevc_intra_pred_luma_vert.s196 vhsub.u8 q13, q13, q11 @(src[2nt-1-row] - src[2nt])>>1
332 vhsub.u8 d26, d26, d22 @(src[2nt-1-row] - src[2nt])>>1
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt1557 # CHECK: vhsub.s8 d16, d16, d17
1559 # CHECK: vhsub.s16 d16, d16, d17
1561 # CHECK: vhsub.s32 d16, d16, d17
1563 # CHECK: vhsub.u8 d16, d16, d17
1565 # CHECK: vhsub.u16 d16, d16, d17
1567 # CHECK: vhsub.u32 d16, d16, d17
1569 # CHECK: vhsub.s8 q8, q8, q9
1571 # CHECK: vhsub.s16 q8, q8, q9
1573 # CHECK: vhsub.s32 q8, q8, q9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneon.txt1557 # CHECK: vhsub.s8 d16, d16, d17
1559 # CHECK: vhsub.s16 d16, d16, d17
1561 # CHECK: vhsub.s32 d16, d16, d17
1563 # CHECK: vhsub.u8 d16, d16, d17
1565 # CHECK: vhsub.u16 d16, d16, d17
1567 # CHECK: vhsub.u32 d16, d16, d17
1569 # CHECK: vhsub.s8 q8, q8, q9
1571 # CHECK: vhsub.s16 q8, q8, q9
1573 # CHECK: vhsub.s32 q8, q8, q9
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt1557 # CHECK: vhsub.s8 d16, d16, d17
1559 # CHECK: vhsub.s16 d16, d16, d17
1561 # CHECK: vhsub.s32 d16, d16, d17
1563 # CHECK: vhsub.u8 d16, d16, d17
1565 # CHECK: vhsub.u16 d16, d16, d17
1567 # CHECK: vhsub.u32 d16, d16, d17
1569 # CHECK: vhsub.s8 q8, q8, q9
1571 # CHECK: vhsub.s16 q8, q8, q9
1573 # CHECK: vhsub.s32 q8, q8, q9
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7775 "xt\004vfma\004vfms\005vfnma\005vfnms\005vhadd\005vhsub\004vins\005vjcvt"
9850 …{ 2007 /* vhsub */, ARM::VHSUBsv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9851 …{ 2007 /* vhsub */, ARM::VHSUBsv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9852 …{ 2007 /* vhsub */, ARM::VHSUBsv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9853 …{ 2007 /* vhsub */, ARM::VHSUBsv2i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9854 …{ 2007 /* vhsub */, ARM::VHSUBsv16i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9855 …{ 2007 /* vhsub */, ARM::VHSUBsv8i8, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEON…
9856 …{ 2007 /* vhsub */, ARM::VHSUBuv8i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9857 …{ 2007 /* vhsub */, ARM::VHSUBuv4i16, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
9858 …{ 2007 /* vhsub */, ARM::VHSUBuv4i32, Convert__Reg1_2__Reg1_2__Reg1_3__CondCode2_0, Feature_HasNEO…
[all …]
/external/vixl/src/aarch32/
Dassembler-aarch32.h4527 void vhsub(
4529 void vhsub(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vhsub() function
4530 vhsub(al, dt, rd, rn, rm); in vhsub()
4533 void vhsub(
4535 void vhsub(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vhsub() function
4536 vhsub(al, dt, rd, rn, rm); in vhsub()
Ddisasm-aarch32.h1840 void vhsub(
1843 void vhsub(
Ddisasm-aarch32.cc4877 void Disassembler::vhsub( in vhsub() function in vixl::aarch32::Disassembler
4888 void Disassembler::vhsub( in vhsub() function in vixl::aarch32::Disassembler
25023 vhsub(CurrentCond(), in DecodeT32()
25054 vhsub(CurrentCond(), in DecodeT32()
38473 vhsub(al, dt, DRegister(rd), DRegister(rn), DRegister(rm)); in DecodeA32()
38500 vhsub(al, dt, QRegister(rd), QRegister(rn), QRegister(rm)); in DecodeA32()
Dassembler-aarch32.cc17905 void Assembler::vhsub( in vhsub() function in vixl::aarch32::Assembler
17932 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm); in vhsub()
17935 void Assembler::vhsub( in vhsub() function in vixl::aarch32::Assembler
17962 Delegate(kVhsub, &Assembler::vhsub, cond, dt, rd, rn, rm); in vhsub()
Dmacro-assembler-aarch32.h7043 vhsub(cond, dt, rd, rn, rm); in Vhsub()
7058 vhsub(cond, dt, rd, rn, rm); in Vhsub()
/external/clang/include/clang/Basic/
Darm_neon.td545 def VHSUB : SInst<"vhsub", "ddd", "csiUcUsUiQcQsQiQUcQUsQUi">;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3642 "vhsub", "s", int_arm_neon_vhsubs, 0>;
3645 "vhsub", "u", int_arm_neon_vhsubu, 0>;
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4685 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4688 "vhsub", "u", int_arm_neon_vhsubu, 0>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td4959 "vhsub", "s", int_arm_neon_vhsubs, 0>;
4962 "vhsub", "u", int_arm_neon_vhsubu, 0>;