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Searched refs:vld2 (Results 1 – 25 of 89) sorted by relevance

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/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvld2.ll17 ;CHECK: vld2.8 {d16, d17}, [r0, :64]
18 %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8(i8* %A, i32 8)
28 ;CHECK: vld2.16 {d16, d17}, [r0, :128]
30 %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16(i8* %tmp0, i32 32)
39 ;CHECK: vld2.32
41 %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32(i8* %tmp0, i32 1)
50 ;CHECK: vld2.32
52 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
62 ;CHECK: vld2.32 {d16, d17}, [r1]!
65 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32(i8* %tmp0, i32 1)
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-vld-encoding.s23 vld2.8 {d16, d17}, [r0, :64]
24 vld2.16 {d16, d17}, [r0, :128]
25 vld2.32 {d16, d17}, [r0]
26 vld2.8 {d16, d17, d18, d19}, [r0, :64]
27 vld2.16 {d16, d17, d18, d19}, [r0, :128]
28 vld2.32 {d16, d17, d18, d19}, [r0, :256]
30 @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf4]
31 @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf4]
32 @ CHECK: vld2.32 {d16, d17}, [r0]@ encoding: [0x8f,0x08,0x60,0xf4]
33 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64]@ encoding: [0x1f,0x03,0x60,0xf4]
[all …]
Dneont2-vld-encoding.s23 @ CHECK: vld2.8 {d16, d17}, [r0, :64] @ encoding: [0x1f,0x08,0x60,0xf9]
24 vld2.8 {d16, d17}, [r0, :64]
25 @ CHECK: vld2.16 {d16, d17}, [r0, :128] @ encoding: [0x6f,0x08,0x60,0xf9]
26 vld2.16 {d16, d17}, [r0, :128]
27 @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x8f,0x08,0x60,0xf9]
28 vld2.32 {d16, d17}, [r0]
29 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0, :64] @ encoding: [0x1f,0x03,0x60,0xf9]
30 vld2.8 {d16, d17, d18, d19}, [r0, :64]
31 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0, :128] @ encoding: [0x6f,0x03,0x60,0xf9]
32 vld2.16 {d16, d17, d18, d19}, [r0, :128]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneont2-vld-encoding.s22 @ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x08]
23 vld2.8 {d16, d17}, [r0:64]
24 @ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x60,0xf9,0x6f,0x08]
25 vld2.16 {d16, d17}, [r0:128]
26 @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x60,0xf9,0x8f,0x08]
27 vld2.32 {d16, d17}, [r0]
28 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x03]
29 vld2.8 {d16, d17, d18, d19}, [r0:64]
30 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x60,0xf9,0x6f,0x03]
31 vld2.16 {d16, d17, d18, d19}, [r0:128]
[all …]
Dneon-vld-encoding.s114 vld2.8 {d16, d17}, [r0:64]
115 vld2.16 {d16, d17}, [r0:128]
116 vld2.32 {d16, d17}, [r0]
117 vld2.8 {d16, d17, d18, d19}, [r0:64]
118 vld2.16 {d16, d17, d18, d19}, [r0:128]
119 vld2.32 {d16, d17, d18, d19}, [r0:256]
121 vld2.8 {d19, d20}, [r0:64]!
122 vld2.16 {d16, d17}, [r0:128]!
123 vld2.32 {q10}, [r0]!
124 vld2.8 {d4-d7}, [r0:64]!
[all …]
Dneon-vld-vst-align.s1666 vld2.8 {d0, d1}, [r4]
1667 vld2.8 {d0, d1}, [r4:16]
1668 vld2.8 {d0, d1}, [r4:32]
1669 vld2.8 {d0, d1}, [r4:64]
1670 vld2.8 {d0, d1}, [r4:128]
1671 vld2.8 {d0, d1}, [r4:256]
1673 @ CHECK: vld2.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x08]
1675 @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]
1678 @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]
1680 @ CHECK: vld2.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x08]
[all …]
/external/llvm/test/MC/ARM/
Dneont2-vld-encoding.s22 @ CHECK: vld2.8 {d16, d17}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x08]
23 vld2.8 {d16, d17}, [r0:64]
24 @ CHECK: vld2.16 {d16, d17}, [r0:128] @ encoding: [0x60,0xf9,0x6f,0x08]
25 vld2.16 {d16, d17}, [r0:128]
26 @ CHECK: vld2.32 {d16, d17}, [r0] @ encoding: [0x60,0xf9,0x8f,0x08]
27 vld2.32 {d16, d17}, [r0]
28 @ CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x03]
29 vld2.8 {d16, d17, d18, d19}, [r0:64]
30 @ CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128] @ encoding: [0x60,0xf9,0x6f,0x03]
31 vld2.16 {d16, d17, d18, d19}, [r0:128]
[all …]
Dneon-vld-encoding.s114 vld2.8 {d16, d17}, [r0:64]
115 vld2.16 {d16, d17}, [r0:128]
116 vld2.32 {d16, d17}, [r0]
117 vld2.8 {d16, d17, d18, d19}, [r0:64]
118 vld2.16 {d16, d17, d18, d19}, [r0:128]
119 vld2.32 {d16, d17, d18, d19}, [r0:256]
121 vld2.8 {d19, d20}, [r0:64]!
122 vld2.16 {d16, d17}, [r0:128]!
123 vld2.32 {q10}, [r0]!
124 vld2.8 {d4-d7}, [r0:64]!
[all …]
Dneon-vld-vst-align.s1666 vld2.8 {d0, d1}, [r4]
1667 vld2.8 {d0, d1}, [r4:16]
1668 vld2.8 {d0, d1}, [r4:32]
1669 vld2.8 {d0, d1}, [r4:64]
1670 vld2.8 {d0, d1}, [r4:128]
1671 vld2.8 {d0, d1}, [r4:256]
1673 @ CHECK: vld2.8 {d0, d1}, [r4] @ encoding: [0x24,0xf9,0x0f,0x08]
1675 @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:16]
1678 @ CHECK-ERRORS: vld2.8 {d0, d1}, [r4:32]
1680 @ CHECK: vld2.8 {d0, d1}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x08]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvld2.ll17 ;CHECK: vld2.8 {d16, d17}, [{{r[0-9]+|lr}}:64]
18 %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8* %A, i32 8)
28 ;CHECK: vld2.16 {d16, d17}, [{{r[0-9]+|lr}}:128]
30 %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8* %tmp0, i32 32)
39 ;CHECK: vld2.32
41 %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8* %tmp0, i32 1)
50 ;CHECK: vld2.32
52 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
62 ;CHECK: vld2.32 {d16, d17}, [{{r[0-9]+|lr}}]!
65 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
[all …]
Darm-vlddup.ll60 ; CHECK: vld2.16 {d16[], d17[]}, [r0]
68 ; CHECK: vld2.32 {d16[], d17[]}, [r0]
84 ; CHECK: vld2.8 {d16[], d17[]}, [r0]
156 ; CHECK: vld2.16 {d16[], d18[]}, [r1]
157 ; CHECK: vld2.16 {d17[], d19[]}, [r1]
165 ; CHECK: vld2.32 {d16[], d18[]}, [r1]
166 ; CHECK: vld2.32 {d17[], d19[]}, [r1]
174 ; CHECK: vld2.8 {d16[], d18[]}, [r1]
175 ; CHECK: vld2.8 {d17[], d19[]}, [r1]
/external/llvm/test/CodeGen/ARM/
Dvld2.ll17 ;CHECK: vld2.8 {d16, d17}, [r0:64]
18 %tmp1 = call %struct.__neon_int8x8x2_t @llvm.arm.neon.vld2.v8i8.p0i8(i8* %A, i32 8)
28 ;CHECK: vld2.16 {d16, d17}, [r0:128]
30 %tmp1 = call %struct.__neon_int16x4x2_t @llvm.arm.neon.vld2.v4i16.p0i8(i8* %tmp0, i32 32)
39 ;CHECK: vld2.32
41 %tmp1 = call %struct.__neon_int32x2x2_t @llvm.arm.neon.vld2.v2i32.p0i8(i8* %tmp0, i32 1)
50 ;CHECK: vld2.32
52 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
62 ;CHECK: vld2.32 {d16, d17}, [r1]!
65 %tmp1 = call %struct.__neon_float32x2x2_t @llvm.arm.neon.vld2.v2f32.p0i8(i8* %tmp0, i32 1)
[all …]
Darm-interleaved-accesses-extract-user.ll4 ; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
22 ; CHECK: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
42 ; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
59 ; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
69 ; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
79 ; CHECK-NOT: %vldN = call { <4 x i32>, <4 x i32> } @llvm.arm.neon.vld2.v4i32.p0i8
/external/capstone/suite/MC/ARM/
Dneon-vld-encoding.s.cs50 0x1f,0x08,0x60,0xf4 = vld2.8 {d16, d17}, [r0:64]
51 0x6f,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]
52 0x8f,0x08,0x60,0xf4 = vld2.32 {d16, d17}, [r0]
53 0x1f,0x03,0x60,0xf4 = vld2.8 {d16, d17, d18, d19}, [r0:64]
54 0x6f,0x03,0x60,0xf4 = vld2.16 {d16, d17, d18, d19}, [r0:128]
55 0xbf,0x03,0x60,0xf4 = vld2.32 {d16, d17, d18, d19}, [r0:256]
56 0x1d,0x38,0x60,0xf4 = vld2.8 {d19, d20}, [r0:64]!
57 0x6d,0x08,0x60,0xf4 = vld2.16 {d16, d17}, [r0:128]!
58 0x8d,0x48,0x60,0xf4 = vld2.32 {d20, d21}, [r0]!
59 0x1d,0x43,0x20,0xf4 = vld2.8 {d4, d5, d6, d7}, [r0:64]!
[all …]
Dneont2-vld-encoding.s.cs10 0x60,0xf9,0x1f,0x08 = vld2.8 {d16, d17}, [r0:64]
11 0x60,0xf9,0x6f,0x08 = vld2.16 {d16, d17}, [r0:128]
12 0x60,0xf9,0x8f,0x08 = vld2.32 {d16, d17}, [r0]
13 0x60,0xf9,0x1f,0x03 = vld2.8 {d16, d17, d18, d19}, [r0:64]
14 0x60,0xf9,0x6f,0x03 = vld2.16 {d16, d17, d18, d19}, [r0:128]
15 0x60,0xf9,0xbf,0x03 = vld2.32 {d16, d17, d18, d19}, [r0:256]
37 0xe0,0xf9,0x3f,0x01 = vld2.8 {d16[1], d17[1]}, [r0:16]
38 0xe0,0xf9,0x5f,0x05 = vld2.16 {d16[1], d17[1]}, [r0:32]
39 0xe0,0xf9,0x8f,0x09 = vld2.32 {d16[1], d17[1]}, [r0]
40 0xe0,0xf9,0x6f,0x15 = vld2.16 {d17[1], d19[1]}, [r0]
[all …]
/external/libhevc/common/arm/
Dihevc_intra_pred_chroma_mode2.s125 vld2.8 {d0,d1},[r0],r8
131 vld2.8 {d2,d3},[r10],r8
134 vld2.8 {d4,d5},[r0],r8
135 vld2.8 {d6,d7},[r10],r8
138 vld2.8 {d8,d9},[r0],r8
139 vld2.8 {d10,d11},[r10],r8
140 vld2.8 {d12,d13},[r0],r8
143 vld2.8 {d14,d15},[r10],r8
189 vld2.8 {d0,d1},[r0],r8
192 vld2.8 {d2,d3},[r10],r8
[all …]
Dihevc_intra_pred_chroma_dc.s129 vld2.s8 {d30,d31}, [r6]! @load from src[nt]
135 vld2.s8 {d26,d27}, [r8]! @load from src[2nt+1]
157 vld2.s8 {d30,d31}, [r6]! @load from src[nt]
161 vld2.s8 {d26,d27}, [r8]! @load from src[2nt+1]
252 vld2.s8 {d30,d31},[r6] @load from src[nt]
255 vld2.s8 {d26,d27},[r8] @load from src[2nt+1]
Dihevc_intra_pred_chroma_ver.s119 vld2.8 {d20,d21}, [r6]! @16 loads (col 0:15)
123 vld2.8 {d22,d23}, [r6] @16 loads (col 16:31)
188 vld2.8 {d20,d21}, [r6]! @16 loads (col 0:15)
192 vld2.8 {d22,d23}, [r6] @16 loads (col 16:31)
/external/libhevc/decoder/arm/
Dihevcd_itrans_recon_dc_chroma.s92 vld2.8 {d2,d3},[r7],r2
93 vld2.8 {d4,d5},[r7],r2
94 vld2.8 {d6,d7},[r7],r2
95 vld2.8 {d8,d9},[r7],r2
97 vld2.8 {d10,d11},[r7],r2
98 vld2.8 {d12,d13},[r7],r2
99 vld2.8 {d14,d15},[r7],r2
100 vld2.8 {d16,d17},[r7]
159 vld2.8 {d2,d3},[r0],r2
160 vld2.8 {d4,d5},[r0],r2
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll29 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
30 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
31 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
32 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
65 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
66 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
67 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
68 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
94 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %0)
95 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
[all …]
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll27 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
28 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
29 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
30 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
63 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %5)
64 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
65 %vld2.fca.1.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 1
66 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld2.fca.0.extract, <4 x i32> %vld2.fca.0.extract)
92 %vld2 = call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2.v4i32.p0i8(i8* %0)
93 %vld2.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld2, 0
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1399 # CHECK: vld2.8 {d16, d17}, [r0:64]
1401 # CHECK: vld2.16 {d16, d17}, [r0:128]
1403 # CHECK: vld2.32 {d16, d17}, [r0]
1405 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
1407 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
1409 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
1457 # CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
1459 # CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
1461 # CHECK: vld2.32 {d16[1], d17[1]}, [r0]
1463 # CHECK: vld2.16 {d17[1], d19[1]}, [r0]
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1399 # CHECK: vld2.8 {d16, d17}, [r0:64]
1401 # CHECK: vld2.16 {d16, d17}, [r0:128]
1403 # CHECK: vld2.32 {d16, d17}, [r0]
1405 # CHECK: vld2.8 {d16, d17, d18, d19}, [r0:64]
1407 # CHECK: vld2.16 {d16, d17, d18, d19}, [r0:128]
1409 # CHECK: vld2.32 {d16, d17, d18, d19}, [r0:256]
1457 # CHECK: vld2.8 {d16[1], d17[1]}, [r0:16]
1459 # CHECK: vld2.16 {d16[1], d17[1]}, [r0:32]
1461 # CHECK: vld2.32 {d16[1], d17[1]}, [r0]
1463 # CHECK: vld2.16 {d17[1], d19[1]}, [r0]
[all …]
/external/libvpx/libvpx/vpx_dsp/arm/
Didct_neon.asm36 vld2.s32 {q0,q1}, [$src]!
37 vld2.s32 {q2,q3}, [$src]!
43 vld2.s16 {$dst0,$dst1,$dst2,$dst3}, [$src]!
/external/libvpx/config/arm-neon/vpx_dsp/arm/
Didct_neon.asm.S38 vld2.s32 {q0,q1}, [\src]!
39 vld2.s32 {q2,q3}, [\src]!
45 vld2.s16 {\dst0,\dst1,\dst2,\dst3}, [\src]!

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