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Searched refs:vld3 (Results 1 – 25 of 66) sorted by relevance

123

/external/capstone/suite/MC/ARM/
Dneon-vld-encoding.s.cs68 0x0f,0x04,0x61,0xf4 = vld3.8 {d16, d17, d18}, [r1]
69 0x4f,0x64,0x22,0xf4 = vld3.16 {d6, d7, d8}, [r2]
70 0x8f,0x14,0x23,0xf4 = vld3.32 {d1, d2, d3}, [r3]
71 0x1f,0x05,0x60,0xf4 = vld3.8 {d16, d18, d20}, [r0:64]
72 0x4f,0xb5,0x64,0xf4 = vld3.16 {d27, d29, d31}, [r4]
73 0x8f,0x65,0x25,0xf4 = vld3.32 {d6, d8, d10}, [r5]
74 0x01,0xc4,0x26,0xf4 = vld3.8 {d12, d13, d14}, [r6], r1
75 0x42,0xb4,0x27,0xf4 = vld3.16 {d11, d12, d13}, [r7], r2
76 0x83,0x24,0x28,0xf4 = vld3.32 {d2, d3, d4}, [r8], r3
77 0x04,0x45,0x29,0xf4 = vld3.8 {d4, d6, d8}, [r9], r4
[all …]
Dneont2-vld-encoding.s.cs16 0x60,0xf9,0x1f,0x04 = vld3.8 {d16, d17, d18}, [r0:64]
17 0x60,0xf9,0x4f,0x04 = vld3.16 {d16, d17, d18}, [r0]
18 0x60,0xf9,0x8f,0x04 = vld3.32 {d16, d17, d18}, [r0]
19 0x60,0xf9,0x1d,0x05 = vld3.8 {d16, d18, d20}, [r0:64]!
20 0x60,0xf9,0x1d,0x15 = vld3.8 {d17, d19, d21}, [r0:64]!
21 0x60,0xf9,0x4d,0x05 = vld3.16 {d16, d18, d20}, [r0]!
22 0x60,0xf9,0x4d,0x15 = vld3.16 {d17, d19, d21}, [r0]!
23 0x60,0xf9,0x8d,0x05 = vld3.32 {d16, d18, d20}, [r0]!
24 0x60,0xf9,0x8d,0x15 = vld3.32 {d17, d19, d21}, [r0]!
42 0xe0,0xf9,0x2f,0x02 = vld3.8 {d16[1], d17[1], d18[1]}, [r0]
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-vld-encoding.s157 vld3.8 {d16, d17, d18}, [r1]
158 vld3.16 {d6, d7, d8}, [r2]
159 vld3.32 {d1, d2, d3}, [r3]
160 vld3.8 {d16, d18, d20}, [r0:64]
161 vld3.u16 {d27, d29, d31}, [r4]
162 vld3.i32 {d6, d8, d10}, [r5]
164 vld3.i8 {d12, d13, d14}, [r6], r1
165 vld3.i16 {d11, d12, d13}, [r7], r2
166 vld3.u32 {d2, d3, d4}, [r8], r3
167 vld3.8 {d4, d6, d8}, [r9], r4
[all …]
Dneont2-vld-encoding.s35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x04]
36 vld3.8 {d16, d17, d18}, [r0:64]
37 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x4f,0x04]
38 vld3.16 {d16, d17, d18}, [r0]
39 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x8f,0x04]
40 vld3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x05]
42 vld3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x15]
44 vld3.8 {d17, d19, d21}, [r0:64]!
[all …]
Dneon-vld-vst-align.s2912 vld3.8 {d0, d1, d2}, [r4]
2913 vld3.8 {d0, d1, d2}, [r4:16]
2914 vld3.8 {d0, d1, d2}, [r4:32]
2915 vld3.8 {d0, d1, d2}, [r4:64]
2916 vld3.8 {d0, d1, d2}, [r4:128]
2917 vld3.8 {d0, d1, d2}, [r4:256]
2919 @ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04]
2921 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]
2924 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]
2926 @ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04]
[all …]
/external/llvm/test/MC/ARM/
Dneon-vld-encoding.s157 vld3.8 {d16, d17, d18}, [r1]
158 vld3.16 {d6, d7, d8}, [r2]
159 vld3.32 {d1, d2, d3}, [r3]
160 vld3.8 {d16, d18, d20}, [r0:64]
161 vld3.u16 {d27, d29, d31}, [r4]
162 vld3.i32 {d6, d8, d10}, [r5]
164 vld3.i8 {d12, d13, d14}, [r6], r1
165 vld3.i16 {d11, d12, d13}, [r7], r2
166 vld3.u32 {d2, d3, d4}, [r8], r3
167 vld3.8 {d4, d6, d8}, [r9], r4
[all …]
Dneont2-vld-encoding.s35 @ CHECK: vld3.8 {d16, d17, d18}, [r0:64] @ encoding: [0x60,0xf9,0x1f,0x04]
36 vld3.8 {d16, d17, d18}, [r0:64]
37 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x4f,0x04]
38 vld3.16 {d16, d17, d18}, [r0]
39 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x60,0xf9,0x8f,0x04]
40 vld3.32 {d16, d17, d18}, [r0]
41 @ CHECK: vld3.8 {d16, d18, d20}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x05]
42 vld3.8 {d16, d18, d20}, [r0:64]!
43 @ CHECK: vld3.8 {d17, d19, d21}, [r0:64]! @ encoding: [0x60,0xf9,0x1d,0x15]
44 vld3.8 {d17, d19, d21}, [r0:64]!
[all …]
Dneon-vld-vst-align.s2912 vld3.8 {d0, d1, d2}, [r4]
2913 vld3.8 {d0, d1, d2}, [r4:16]
2914 vld3.8 {d0, d1, d2}, [r4:32]
2915 vld3.8 {d0, d1, d2}, [r4:64]
2916 vld3.8 {d0, d1, d2}, [r4:128]
2917 vld3.8 {d0, d1, d2}, [r4:256]
2919 @ CHECK: vld3.8 {d0, d1, d2}, [r4] @ encoding: [0x24,0xf9,0x0f,0x04]
2921 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:16]
2924 @ CHECK-ERRORS: vld3.8 {d0, d1, d2}, [r4:32]
2926 @ CHECK: vld3.8 {d0, d1, d2}, [r4:64] @ encoding: [0x24,0xf9,0x1f,0x04]
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-vld-encoding.s38 vld3.8 {d16, d17, d18}, [r0, :64]
39 vld3.16 {d16, d17, d18}, [r0]
40 vld3.32 {d16, d17, d18}, [r0]
41 vld3.8 {d16, d18, d20}, [r0, :64]!
42 vld3.8 {d17, d19, d21}, [r0, :64]!
43 vld3.16 {d16, d18, d20}, [r0]!
44 vld3.16 {d17, d19, d21}, [r0]!
45 vld3.32 {d16, d18, d20}, [r0]!
46 vld3.32 {d17, d19, d21}, [r0]!
48 @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf4]
[all …]
Dneont2-vld-encoding.s36 @ CHECK: vld3.8 {d16, d17, d18}, [r0, :64] @ encoding: [0x1f,0x04,0x60,0xf9]
37 vld3.8 {d16, d17, d18}, [r0, :64]
38 @ CHECK: vld3.16 {d16, d17, d18}, [r0] @ encoding: [0x4f,0x04,0x60,0xf9]
39 vld3.16 {d16, d17, d18}, [r0]
40 @ CHECK: vld3.32 {d16, d17, d18}, [r0] @ encoding: [0x8f,0x04,0x60,0xf9]
41 vld3.32 {d16, d17, d18}, [r0]
42 @ CHECK: vld3.8 {d16, d18, d20}, [r0, :64]! @ encoding: [0x1d,0x05,0x60,0xf9]
43 vld3.8 {d16, d18, d20}, [r0, :64]!
44 @ CHECK: vld3.8 {d17, d19, d21}, [r0, :64]! @ encoding: [0x1d,0x15,0x60,0xf9]
45 vld3.8 {d17, d19, d21}, [r0, :64]!
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvld3.ll18 ;CHECK: vld3.8 {d16, d17, d18}, [r0, :64]
19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A, i32 32)
28 ;CHECK: vld3.16
30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16(i8* %tmp0, i32 1)
54 ;CHECK: vld3.32
56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %tmp0, i32 1)
65 ;CHECK: vld3.32
67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32(i8* %tmp0, i32 1)
[all …]
D2010-05-20-NEONSpillCrash.ll4 ; the @llvm.arm.neon.vld3.v8i8 defined three parts of a register.
8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8*, i32) nounwind readonly
13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A2, i32 1) ; <%struct.__neon…
16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A4, i32 1) ; <%struct.__neon…
19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A5, i32 1) ; <%struct.__neon…
21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A6, i32 1) ; <%struct.__neon…
23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A7, i32 1) ; <%struct.__neon…
26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8(i8* %A8, i32 1) ; <%struct.__neon…
/external/llvm/test/CodeGen/ARM/
Dvld3.ll18 ;CHECK: vld3.8 {d16, d17, d18}, [r0:64]
19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32)
28 ;CHECK: vld3.16
30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+}}], {{r[0-9]+}}
43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
54 ;CHECK: vld3.32
56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1)
65 ;CHECK: vld3.32
67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1)
[all …]
D2010-05-20-NEONSpillCrash.ll4 ; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register.
8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct._…
16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._…
19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct._…
21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._…
23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct._…
26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct._…
D2012-08-27-CopyPhysRegCrash.ll8 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind reado…
22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1)
25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1)
27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1)
31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
Darm-interleaved-accesses.ll17 ; NEON: vld3.32 {d16, d17, d18}, [r0]
19 ; NONEON-NOT: vld3
96 ; NEON: vld3.32 {d16, d17, d18}, [r0]
98 ; NONEON-NOT: vld3
177 ; NEON: vld3.32 {d16, d18, d20}, [r0]!
178 ; NEON: vld3.32 {d17, d19, d21}, [r0]
180 ; NONEON-NOT: vld3
246 ; NEON: vld3.32
248 ; NONEON-NOT: vld3
Dvld-vst-upgrade.ll28 ; CHECK: vld3.32 {d16, d17, d18}, [r1]
30 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1)
34 declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly
57 ; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvld3.ll18 ;CHECK: vld3.8 {d16, d17, d18}, [{{r[0-9]+|lr}}:64]
19 %tmp1 = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A, i32 32)
28 ;CHECK: vld3.16
30 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
40 ;CHECK: vld3.16 {d16, d17, d18}, [{{r[0-9]+|lr}}], {{r[0-9]+|lr}}
43 %tmp1 = call %struct.__neon_int16x4x3_t @llvm.arm.neon.vld3.v4i16.p0i8(i8* %tmp0, i32 1)
54 ;CHECK: vld3.32
56 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32.p0i8(i8* %tmp0, i32 1)
65 ;CHECK: vld3.32
67 %tmp1 = call %struct.__neon_float32x2x3_t @llvm.arm.neon.vld3.v2f32.p0i8(i8* %tmp0, i32 1)
[all …]
D2010-05-20-NEONSpillCrash.ll4 ; the @llvm.arm.neon.vld3.v8i8.p0i8 defined three parts of a register.
8 declare %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8*, i32) nounwind readonly
13 …%tmp1b = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A2, i32 1) ; <%struct._…
16 …%tmp1d = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A4, i32 1) ; <%struct._…
19 …%tmp1e = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A5, i32 1) ; <%struct._…
21 …%tmp1f = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A6, i32 1) ; <%struct._…
23 …%tmp1g = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A7, i32 1) ; <%struct._…
26 …%tmp1h = call %struct.__neon_int8x8x3_t @llvm.arm.neon.vld3.v8i8.p0i8(i8* %A8, i32 1) ; <%struct._…
Darm-insert-subvector.ll9 ; CHECK: vld3.32 {d16, d17, d18}, [r0]
17 ; CHECK: vld3.32 {d16, d17, d18}, [r0]
34 ; CHECK: vld3.8 {d16, d17, d18}, [r0]
Darm-vlddup.ll92 ; CHECK: vld3.16 {d16[], d17[], d18[]}, [r1]
100 ; CHECK: vld3.32 {d16[], d17[], d18[]}, [r1]
116 ; CHECK: vld3.8 {d16[], d17[], d18[]}, [r1]
183 ; CHECK: vld3.16 {d16[], d18[], d20[]}, [r1]
184 ; CHECK: vld3.16 {d17[], d19[], d21[]}, [r1]
192 ; CHECK: vld3.32 {d16[], d18[], d20[]}, [r1]
193 ; CHECK: vld3.32 {d17[], d19[], d21[]}, [r1]
201 ; CHECK: vld3.8 {d16[], d18[], d20[]}, [r1]
202 ; CHECK: vld3.8 {d17[], d19[], d21[]}, [r1]
D2012-08-27-CopyPhysRegCrash.ll8 declare { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8*, i32) nounwind reado…
22 %7 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* null, i32 1)
25 %10 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %9, i32 1)
27 %12 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %6, i32 1)
31 %16 = tail call { <16 x i8>, <16 x i8>, <16 x i8> } @llvm.arm.neon.vld3.v16i8.p0i8(i8* %15, i32 1)
Dvld-vst-upgrade.ll28 ; CHECK: vld3.32 {d16, d17, d18}, [r1]
30 %tmp1 = call %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8* %ptr, i32 1)
34 declare %struct.__neon_int32x2x3_t @llvm.arm.neon.vld3.v2i32(i8*, i32) nounwind readonly
57 ; CHECK: vld3.32 {d16[1], d17[1], d18[1]}, [r1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll170 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
171 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
172 %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2
173 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
207 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
208 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
209 %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1
210 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)
/external/llvm/test/Transforms/EarlyCSE/AArch64/
Dintrinsics.ll168 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
169 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
170 %vld3.fca.2.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 2
171 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.2.extract)
205 %vld3 = call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3.v4i32.p0i8(i8* %5)
206 %vld3.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 0
207 %vld3.fca.1.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld3, 1
208 %call = call <4 x i32> @vaddq_s32(<4 x i32> %vld3.fca.0.extract, <4 x i32> %vld3.fca.0.extract)

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