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Searched refs:vmem (Results 1 – 25 of 75) sorted by relevance

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/external/llvm/test/MC/Hexagon/
Dv60-vmem.s5 #CHECK: 292cc11b { vmem(r12++#1) = v27 }
7 vmem(r12++#1)=v27
10 #CHECK: 294dc319 { v25 = vmem(r13++#3):nt }
12 v25=vmem(r13++#3):nt
20 #CHECK: 291dc01f { v31 = vmem(r29++#0) }
22 v31=vmem(r29++#0)
30 #CHECK: 296ec411 { vmem(r14++#-4):nt = v17 }
32 vmem(r14++#-4):nt=v17
35 #CHECK: 29fec62f { if (!p0) vmem(r30++#-2):nt = v15 }
37 if (!p0) vmem(r30++#-2):nt=v15
[all …]
Dv60-misc.s62 # CHECK: 2800c00f { v15 = vmem(r0+#0) }
63 v15 = vmem(r0)
65 # CHECK: 2841c010 { v16 = vmem(r1+#0):nt }
66 v16 = vmem(r1):nt
68 # CHECK: 2822c011 { vmem(r2+#0) = v17 }
69 vmem(r2) = v17
71 # CHECK: 2863c012 { vmem(r3+#0):nt = v18 }
72 vmem(r3):nt = v18
74 # CHECK: 2884c013 { if (q0) vmem(r4+#0) = v19 }
75 if (q0) vmem(r4) = v19
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Hexagon/
Dv60-vmem.s5 #CHECK: 292cc11b { vmem(r12++#1) = v27 }
7 vmem(r12++#1)=v27
10 #CHECK: 294dc319 { v25 = vmem(r13++#3):nt }
12 v25=vmem(r13++#3):nt
20 #CHECK: 291dc01f { v31 = vmem(r29++#0) }
22 v31=vmem(r29++#0)
30 #CHECK: 296ec411 { vmem(r14++#-4):nt = v17 }
32 vmem(r14++#-4):nt=v17
35 #CHECK: 29fec62f { if (!p0) vmem(r30++#-2):nt = v15 }
37 if (!p0) vmem(r30++#-2):nt=v15
[all …]
Dv62_all.s122 if (!P0) V0.cur=vmem(R0+#04)
125 # CHECK: 2880c4a0 if (!p0) v0.cur = vmem(r0+#4) }
131 if (!P0) V0.cur=vmem(R0++#03)
134 # CHECK: 2980c3a0 if (!p0) v0.cur = vmem(r0++#3) }
140 if (!P0) V0.cur=vmem(R0++M0)
143 # CHECK: 2b80c0a0 if (!p0) v0.cur = vmem(r0++m0) }
149 if (P0) V0.cur=vmem(R0+#04)
152 # CHECK: 2880c480 if (p0) v0.cur = vmem(r0+#4) }
158 if (P0) V0.cur=vmem(R0++#03)
161 # CHECK: 2980c380 if (p0) v0.cur = vmem(r0++#3) }
[all …]
Dv60-misc.s62 # CHECK: 2800c00f { v15 = vmem(r0+#0) }
63 v15 = vmem(r0)
65 # CHECK: 2841c010 { v16 = vmem(r1+#0):nt }
66 v16 = vmem(r1):nt
68 # CHECK: 2822c011 { vmem(r2+#0) = v17 }
69 vmem(r2) = v17
71 # CHECK: 2863c012 { vmem(r3+#0):nt = v18 }
72 vmem(r3):nt = v18
74 # CHECK: 2884c013 { if (q0) vmem(r4+#0) = v19 }
75 if (q0) vmem(r4) = v19
[all …]
Dvscatter-slot.s8 v1=vmem(r1+#0)
13 v1=vmem(r3+#0)
16 # CHECK: vmem(r4+#0):scatter_release
18 v1=vmem(r5+#0)
19 vmem(r4+#0):scatter_release
21 # CHECK: vmem(r4+#0):scatter_release
23 v1=vmem(r5+#0)
24 vmem(r4+#0):scatter_release
Dv65_all.s41 vmem(R0+#0):scatter_release
42 # CHECK: 2820c028 { vmem(r0+#0):scatter_release }
56 vmem(R0++M0):scatter_release
57 # CHECK: 2b20c028 { vmem(r0++m0):scatter_release }
106 vmem(R0++#0):scatter_release
107 # CHECK: 2920c028 { vmem(r0++#0):scatter_release }
/external/libaom/libaom/aom_ports/
Dmem_ops.h66 static unsigned MEM_VALUE_T mem_get_be16(const void *vmem) { in mem_get_be16() argument
68 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be16()
77 static unsigned MEM_VALUE_T mem_get_be24(const void *vmem) { in mem_get_be24() argument
79 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be24()
89 static unsigned MEM_VALUE_T mem_get_be32(const void *vmem) { in mem_get_be32() argument
91 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be32()
102 static unsigned MEM_VALUE_T mem_get_le16(const void *vmem) { in mem_get_le16() argument
104 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_le16()
113 static unsigned MEM_VALUE_T mem_get_le24(const void *vmem) { in mem_get_le24() argument
115 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_le24()
[all …]
Dmem_ops_aligned.h49 const void *vmem) { \
50 const uint##sz##_t *mem = (const uint##sz##_t *)vmem; \
56 const void *vmem) { \
57 const int##sz##_t *mem = (const int##sz##_t *)vmem; \
63 const void *vmem) { \
64 const uint##sz##_t *mem = (const uint##sz##_t *)vmem; \
72 const void *vmem) { \
73 const int##sz##_t *mem = (const int##sz##_t *)vmem; \
80 static AOM_INLINE void mem_put_##end##sz##_aligned(void *vmem, \
82 uint##sz##_t *mem = (uint##sz##_t *)vmem; \
[all …]
/external/libvpx/libvpx/vpx_ports/
Dmem_ops.h65 static unsigned MEM_VALUE_T mem_get_be16(const void *vmem) { in mem_get_be16() argument
67 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be16()
76 static unsigned MEM_VALUE_T mem_get_be24(const void *vmem) { in mem_get_be24() argument
78 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be24()
88 static unsigned MEM_VALUE_T mem_get_be32(const void *vmem) { in mem_get_be32() argument
90 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_be32()
101 static unsigned MEM_VALUE_T mem_get_le16(const void *vmem) { in mem_get_le16() argument
103 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_le16()
112 static unsigned MEM_VALUE_T mem_get_le24(const void *vmem) { in mem_get_le24() argument
114 const MAU_T *mem = (const MAU_T *)vmem; in mem_get_le24()
[all …]
Dmem_ops_aligned.h48 const void *vmem) { \
49 const uint##sz##_t *mem = (const uint##sz##_t *)vmem; \
55 const void *vmem) { \
56 const int##sz##_t *mem = (const int##sz##_t *)vmem; \
62 const void *vmem) { \
63 const uint##sz##_t *mem = (const uint##sz##_t *)vmem; \
71 const void *vmem) { \
72 const int##sz##_t *mem = (const int##sz##_t *)vmem; \
79 static VPX_INLINE void mem_put_##end##sz##_aligned(void *vmem, \
81 uint##sz##_t *mem = (uint##sz##_t *)vmem; \
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/
Disel-expand-unaligned-loads.ll4 ; CHECK-DAG: v[[V00:[0-9]+]] = vmem(r[[B00:[0-9]+]]+#0)
5 ; CHECK-DAG: v[[V01:[0-9]+]] = vmem(r[[B00]]+#1)
14 ; CHECK-DAG: v[[V10:[0-9]+]] = vmem(r[[B01:[0-9]+]]+#0)
15 ; CHECK-DAG: v[[V11:[0-9]+]] = vmem(r[[B01]]+#1)
16 ; CHECK-DAG: v[[V12:[0-9]+]] = vmem(r[[B01]]+#2)
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv6vect-dbl.ll10 ; CHECKO0: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
11 ; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
12 ; CHECKO0: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
15 ; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)
16 ; CHECKO2: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
17 ; CHECKO2: v{{[0-9].*}} = vmem(r{{[0-9]*}}+#0)
20 ; CHECK: vmem(r{{[0-9]*}}+#0) = v{{[0-9]*}}
21 ; CHECK: vmem(r{{[0-9]*}}+#32) = v{{[0-9]*}}
22 ; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#0)
23 ; CHECK: v{{[0-9]*}} = vmem(r{{[0-9]*}}+#32)
[all …]
Dv6vassignp.ll3 ; CHECK: vmem
4 ; CHECK: vmem
5 ; CHECK: vmem
6 ; CHECK: vmem
Dhvx-nontemporal.ll7 ; CHECK: v0 = vmem(r0+#7):nt
11 ; CHECK: v1.cur = vmem(r2+#0):nt
14 ; CHECK: vmem(r3+#3):nt = v1
18 ; CHECK: vmem(r2+#0):nt = v0
Dvec-call-full1.ll3 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
4 ; CHECK-DAG: v{{[0-9]+}} = vmem(r{{[0-9]+}}+#0)
5 ; CHECK-DAG: vmem(r{{[0-9]+}}+#{{[0-1]}}) = v{{[0-9]+}}
6 ; CHECK-DAG: vmem(r{{[0-9]+}}+#{{[0-1]}}) = v{{[0-9]+}}
Dv6vect-dbl-fail1.ll2 ; CHECK: vmem
3 ; CHECK: vmem
5 ; CHECK: vmem
6 ; CHECK: vmem
Dhvx-byte-store.ll6 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
19 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
32 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
45 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
Dhvx-byte-store-double.ll6 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
19 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
32 ; CHECK: if (q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
45 ; CHECK: if (!q{{[0-3]}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
Dv6vec_inc1.ll6 ; CHECK-DAG: v{{[0-9]*}} = vmem(r{{[0-9]*}}++#1)
7 ; CHECK-DAG: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new
12 ; CHECK-DAG-SWP: v{{[0-9]*}}.cur = vmem(r{{[0-9]*}}++#1)
13 ; CHECK-DAG-SWP: vmem(r{{[0-9]*}}++#1) = v{{[0-9]*}}.new
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dv65-gather.ll5 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
8 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
11 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
14 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
17 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
20 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
Dv65-gather-double.ll5 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
8 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
11 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
14 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
17 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
20 ; CHECK: vmem(r{{[0-9]+}}+#0) = vtmp.new
Dbyte-store.ll4 ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
7 ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
10 ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
13 ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
Dbyte-store-double.ll4 ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
7 ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0) = v{{[0-9]+}}
10 ; CHECK: if (q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
13 ; CHECK: if (!q{{[0-3]+}}) vmem(r{{[0-9]+}}+#0):nt = v{{[0-9]+}}
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV60.td69 def V6_vL32b_ai : T_vload_ai <"$dst = vmem($src1+#$src2)">,
71 def V6_vL32b_nt_ai : T_vload_ai <"$dst = vmem($src1+#$src2):nt">,
74 def V6_vL32b_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2)">,
76 def V6_vL32b_nt_ai_128B : T_vload_ai_128B <"$dst = vmem($src1+#$src2):nt">,
89 def V6_vL32b_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2)">,
91 def V6_vL32b_nt_cur_ai : T_vload_ai <"$dst.cur = vmem($src1+#$src2):nt">,
95 <"$dst.cur = vmem($src1+#$src2)">,
98 <"$dst.cur = vmem($src1+#$src2):nt">,
104 def V6_vL32b_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2)">,
106 def V6_vL32b_nt_tmp_ai : T_vload_ai <"$dst.tmp = vmem($src1+#$src2):nt">,
[all …]

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