| /external/swiftshader/third_party/LLVM/test/MC/ARM/ |
| D | neont2-mul-accum-encoding.s | 80 vqdmlsl.s16 q8, d19, d18
81 vqdmlsl.s32 q8, d19, d18
83 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b]
84 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b]
|
| D | neon-mul-accum-encoding.s | 63 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2]
64 vqdmlsl.s16 q8, d19, d18
65 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2]
66 vqdmlsl.s32 q8, d19, d18
|
| D | neon-mul-encoding.s | 78 vqdmlsl.s16 q8, d19, d18
79 vqdmlsl.s32 q8, d19, d18
81 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2]
82 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2]
|
| /external/llvm/test/MC/ARM/ |
| D | neon-mul-accum-encoding.s | 90 vqdmlsl.s16 q8, d19, d18
91 vqdmlsl.s32 q8, d19, d18
93 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2]
94 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2]
|
| D | neont2-mul-accum-encoding.s | 96 vqdmlsl.s16 q8, d19, d18
97 vqdmlsl.s32 q8, d19, d18
99 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b]
100 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | neon-mul-accum-encoding.s | 90 vqdmlsl.s16 q8, d19, d18
91 vqdmlsl.s32 q8, d19, d18
93 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xa2,0x0b,0xd3,0xf2]
94 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xa2,0x0b,0xe3,0xf2]
|
| D | neont2-mul-accum-encoding.s | 96 vqdmlsl.s16 q8, d19, d18
97 vqdmlsl.s32 q8, d19, d18
99 @ CHECK: vqdmlsl.s16 q8, d19, d18 @ encoding: [0xd3,0xef,0xa2,0x0b]
100 @ CHECK: vqdmlsl.s32 q8, d19, d18 @ encoding: [0xe3,0xef,0xa2,0x0b]
|
| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | vqdmul.ll | 243 ;CHECK: vqdmlsl.s16
247 …%tmp4 = call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %tmp1, <4 x i16> %tmp2, <4 x i16> %t…
253 ;CHECK: vqdmlsl.s32
257 …%tmp4 = call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %tmp1, <2 x i32> %tmp2, <2 x i32> %t…
264 ; CHECK: vqdmlsl.s16 q0, d2, d3[1]
266 …%1 = tail call <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32> %arg0_int32x4_t, <4 x i16> %arg1_i…
273 ; CHECK: vqdmlsl.s32 q0, d2, d3[1]
275 …%1 = tail call <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64> %arg0_int64x2_t, <2 x i32> %arg1_i…
279 declare <4 x i32> @llvm.arm.neon.vqdmlsl.v4i32(<4 x i32>, <4 x i16>, <4 x i16>) nounwind readnone
280 declare <2 x i64> @llvm.arm.neon.vqdmlsl.v2i64(<2 x i64>, <2 x i32>, <2 x i32>) nounwind readnone
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-mul-accum-encoding.s.cs | 38 0xa2,0x0b,0xd3,0xf2 = vqdmlsl.s16 q8, d19, d18
39 0xa2,0x0b,0xe3,0xf2 = vqdmlsl.s32 q8, d19, d18
|
| D | neont2-mul-accum-encoding.s.cs | 40 0xd3,0xef,0xa2,0x0b = vqdmlsl.s16 q8, d19, d18
41 0xe3,0xef,0xa2,0x0b = vqdmlsl.s32 q8, d19, d18
|
| /external/arm-neon-tests/ |
| D | ref_vqdmlsl.c | 26 #define INSN_NAME vqdmlsl
|
| D | Makefile.gcc | 46 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| D | Makefile | 40 vqsub vqdmulh_lane vqdmull vqdmlal vqdmlsl vceq vcge vcle \
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | vqdmul.ll | 247 ;CHECK: vqdmlsl.s16
258 ;CHECK: vqdmlsl.s32
270 ; CHECK: vqdmlsl.s16 q0, d2, d3[1]
280 ; CHECK: vqdmlsl.s32 q0, d2, d3[1]
|
| /external/llvm/test/CodeGen/ARM/ |
| D | vqdmul.ll | 247 ;CHECK: vqdmlsl.s16
258 ;CHECK: vqdmlsl.s32
270 ; CHECK: vqdmlsl.s16 q0, d2, d3[1]
280 ; CHECK: vqdmlsl.s32 q0, d2, d3[1]
|
| /external/clang/include/clang/Basic/ |
| D | arm_neon.td | 372 def OP_QDMLSL_LN : Op<(call "vqdmlsl", $p0, $p1, (splat $p2, $p3))>;
373 def OP_QDMLSLHi_LN : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
446 def OP_QDMLSLHi : Op<(call "vqdmlsl", $p0, (call "vget_high", $p1),
534 def VQDMLSL : SInst<"vqdmlsl", "wwdd", "si">;
1581 def SCALAR_SQDMLSL : SInst<"vqdmlsl", "rrss", "SsSi">;
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 5259 void vqdmlsl(
5261 void vqdmlsl(DataType dt, QRegister rd, DRegister rn, DRegister rm) { in vqdmlsl() function
5262 vqdmlsl(al, dt, rd, rn, rm); in vqdmlsl()
5265 void vqdmlsl(Condition cond,
5271 void vqdmlsl( in vqdmlsl() function
5273 vqdmlsl(al, dt, rd, rn, dm, index); in vqdmlsl()
|
| D | disasm-aarch32.h | 2167 void vqdmlsl(
2170 void vqdmlsl(Condition cond,
|
| /external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 650 # CHECK: vqdmlsl.s16 q8, d19, d18
652 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| D | neon.txt | 753 # CHECK: vqdmlsl.s16 q8, d19, d18
755 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 650 # CHECK: vqdmlsl.s16 q8, d19, d18
652 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| D | neon.txt | 753 # CHECK: vqdmlsl.s16 q8, d19, d18
755 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| /external/llvm/test/MC/Disassembler/ARM/ |
| D | neont2.txt | 650 # CHECK: vqdmlsl.s16 q8, d19, d18
652 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| D | neon.txt | 753 # CHECK: vqdmlsl.s16 q8, d19, d18
755 # CHECK: vqdmlsl.s32 q8, d19, d18
|
| /external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 3619 "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
3620 defm VQDMLSLsl: N3VLInt3SL_HS<0, 0b111, "vqdmlsl", "s", int_arm_neon_vqdmlsl>;
|