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Searched refs:vqrdmulh (Results 1 – 25 of 43) sorted by relevance

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/external/llvm/test/CodeGen/ARM/
Dneon-v8.1a.ll6 declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
7 declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
8 declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
23 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
31 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
39 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
47 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
55 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
63 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
[all …]
Dvqdmul.ll85 ;CHECK: vqrdmulh.s16
88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
94 ;CHECK: vqrdmulh.s32
97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
103 ;CHECK: vqrdmulh.s16
106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
112 ;CHECK: vqrdmulh.s32
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
122 ; CHECK: vqrdmulh.s16 q0, q0, d2[1]
124 …%1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; …
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dneon-v8.1a.ll6 declare <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16>, <4 x i16>)
7 declare <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16>, <8 x i16>)
8 declare <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32>, <2 x i32>)
9 declare <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32>, <4 x i32>)
23 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
31 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
39 %prod = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %mhs, <2 x i32> %rhs)
47 %prod = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %mhs, <4 x i32> %rhs)
55 %prod = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %mhs, <4 x i16> %rhs)
63 %prod = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %mhs, <8 x i16> %rhs)
[all …]
Dvqdmul.ll85 ;CHECK: vqrdmulh.s16
88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
94 ;CHECK: vqrdmulh.s32
97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
103 ;CHECK: vqrdmulh.s16
106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
112 ;CHECK: vqrdmulh.s32
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
122 ; CHECK: vqrdmulh.s16 q0, q0, d2[1]
124 …%1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; …
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-mul-encoding.s33 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
34 vqrdmulh.s16 d16, d16, d17
35 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
36 vqrdmulh.s32 d16, d16, d17
37 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
38 vqrdmulh.s16 q8, q8, q9
39 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
40 vqrdmulh.s32 q8, q8, q9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneont2-mul-encoding.s43 vqrdmulh.s16 d16, d16, d17
44 vqrdmulh.s32 d16, d16, d17
45 vqrdmulh.s16 q8, q8, q9
46 vqrdmulh.s32 q8, q8, q9
48 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
Dneon-mul-encoding.s71 vqrdmulh.s16 d16, d16, d17
72 vqrdmulh.s32 d16, d16, d17
73 vqrdmulh.s16 q8, q8, q9
74 vqrdmulh.s32 q8, q8, q9
76 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3]
77 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3]
78 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3]
79 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3]
/external/llvm/test/MC/ARM/
Dneont2-mul-encoding.s43 vqrdmulh.s16 d16, d16, d17
44 vqrdmulh.s32 d16, d16, d17
45 vqrdmulh.s16 q8, q8, q9
46 vqrdmulh.s32 q8, q8, q9
48 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0x50,0xff,0xa1,0x0b]
49 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0x60,0xff,0xa1,0x0b]
50 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0x50,0xff,0xe2,0x0b]
51 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0x60,0xff,0xe2,0x0b]
Dneon-mul-encoding.s71 vqrdmulh.s16 d16, d16, d17
72 vqrdmulh.s32 d16, d16, d17
73 vqrdmulh.s16 q8, q8, q9
74 vqrdmulh.s32 q8, q8, q9
76 @ CHECK: vqrdmulh.s16 d16, d16, d17 @ encoding: [0xa1,0x0b,0x50,0xf3]
77 @ CHECK: vqrdmulh.s32 d16, d16, d17 @ encoding: [0xa1,0x0b,0x60,0xf3]
78 @ CHECK: vqrdmulh.s16 q8, q8, q9 @ encoding: [0xe2,0x0b,0x50,0xf3]
79 @ CHECK: vqrdmulh.s32 q8, q8, q9 @ encoding: [0xe2,0x0b,0x60,0xf3]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvqdmul.ll85 ;CHECK: vqrdmulh.s16
88 %tmp3 = call <4 x i16> @llvm.arm.neon.vqrdmulh.v4i16(<4 x i16> %tmp1, <4 x i16> %tmp2)
94 ;CHECK: vqrdmulh.s32
97 %tmp3 = call <2 x i32> @llvm.arm.neon.vqrdmulh.v2i32(<2 x i32> %tmp1, <2 x i32> %tmp2)
103 ;CHECK: vqrdmulh.s16
106 %tmp3 = call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %tmp1, <8 x i16> %tmp2)
112 ;CHECK: vqrdmulh.s32
115 %tmp3 = call <4 x i32> @llvm.arm.neon.vqrdmulh.v4i32(<4 x i32> %tmp1, <4 x i32> %tmp2)
122 ; CHECK: vqrdmulh.s16 q0, q0, d2[1]
124 …%1 = tail call <8 x i16> @llvm.arm.neon.vqrdmulh.v8i16(<8 x i16> %arg0_int16x8_t, <8 x i16> %0) ; …
[all …]
/external/capstone/suite/MC/ARM/
Dneont2-mul-encoding.s.cs18 0x50,0xff,0xa1,0x0b = vqrdmulh.s16 d16, d16, d17
19 0x60,0xff,0xa1,0x0b = vqrdmulh.s32 d16, d16, d17
20 0x50,0xff,0xe2,0x0b = vqrdmulh.s16 q8, q8, q9
21 0x60,0xff,0xe2,0x0b = vqrdmulh.s32 q8, q8, q9
Dneon-mul-encoding.s.cs32 0xa1,0x0b,0x50,0xf3 = vqrdmulh.s16 d16, d16, d17
33 0xa1,0x0b,0x60,0xf3 = vqrdmulh.s32 d16, d16, d17
34 0xe2,0x0b,0x50,0xf3 = vqrdmulh.s16 q8, q8, q9
35 0xe2,0x0b,0x60,0xf3 = vqrdmulh.s32 q8, q8, q9
/external/arm-neon-tests/
Dref_vqrdmulh_n.c34 #define INSN vqrdmulh
DMakefile.gcc51 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
Dref_vqrdmulh_lane.c34 #define INSN vqrdmulh
Dref_vqrdmulh.c34 #define INSN vqrdmulh
DMakefile45 vshr_n vsra_n vtrn vuzp vzip vreinterpret vqdmulh vqrdmulh \
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon-tests.txt45 # CHECK: vqrdmulh.s32 d0, d0, d3[1]
Dneont2.txt683 # CHECK: vqrdmulh.s16 d16, d16, d17
685 # CHECK: vqrdmulh.s32 d16, d16, d17
687 # CHECK: vqrdmulh.s16 q8, q8, q9
689 # CHECK: vqrdmulh.s32 q8, q8, q9
Dneon.txt787 # CHECK: vqrdmulh.s16 d16, d16, d17
789 # CHECK: vqrdmulh.s32 d16, d16, d17
791 # CHECK: vqrdmulh.s16 q8, q8, q9
793 # CHECK: vqrdmulh.s32 q8, q8, q9
/external/llvm/test/MC/Disassembler/ARM/
Dneon-tests.txt45 # CHECK: vqrdmulh.s32 d0, d0, d3[1]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneon-tests.txt45 # CHECK: vqrdmulh.s32 d0, d0, d3[1]
/external/clang/include/clang/Basic/
Darm_neon.td376 def OP_QRDMULH_LN : Op<(call "vqrdmulh", $p0, (splat $p1, $p2))>;
377 def OP_QRDMLAH : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, $p2))>;
378 def OP_QRDMLSH : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, $p2))>;
379 def OP_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
380 def OP_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1, (splat $p2, $p3)))>;
479 def OP_SCALAR_QRDMULH_LN : ScalarMulOp<"vqrdmulh">;
481 def OP_SCALAR_QRDMLAH_LN : Op<(call "vqadd", $p0, (call "vqrdmulh", $p1,
483 def OP_SCALAR_QRDMLSH_LN : Op<(call "vqsub", $p0, (call "vqrdmulh", $p1,
526 def VQRDMULH : SInst<"vqrdmulh", "ddd", "siQsQi">;
1438 def SCALAR_SQRDMULH : SInst<"vqrdmulh", "sss", "SsSi">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h5337 void vqrdmulh(
5339 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegister rm) { in vqrdmulh() function
5340 vqrdmulh(al, dt, rd, rn, rm); in vqrdmulh()
5343 void vqrdmulh(
5345 void vqrdmulh(DataType dt, QRegister rd, QRegister rn, QRegister rm) { in vqrdmulh() function
5346 vqrdmulh(al, dt, rd, rn, rm); in vqrdmulh()
5349 void vqrdmulh(Condition cond,
5354 void vqrdmulh(DataType dt, DRegister rd, DRegister rn, DRegisterLane rm) { in vqrdmulh() function
5355 vqrdmulh(al, dt, rd, rn, rm); in vqrdmulh()
5358 void vqrdmulh(Condition cond,
[all …]
Ddisasm-aarch32.h2212 void vqrdmulh(
2215 void vqrdmulh(
2218 void vqrdmulh(Condition cond,
2224 void vqrdmulh(Condition cond,

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