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Searched refs:vregs (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegAllocPBQP.cpp195 const RegSet &vregs) { in build() argument
218 for (RegSet::const_iterator vregItr = vregs.begin(), vregEnd = vregs.end(); in build()
285 for (RegSet::const_iterator vr1Itr = vregs.begin(), vrEnd = vregs.end(); in build()
341 const RegSet &vregs) { in build() argument
343 std::auto_ptr<PBQPRAProblem> p = PBQPBuilder::build(mf, lis, loopInfo, vregs); in build()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRegAllocPBQP.h130 const RegSet &vregs);
151 const RegSet &vregs);
/external/elfutils/backends/
Daarch64_initreg.c85 dwarf_fregs[r] = fregs.vregs[r] & 0xFFFFFFFF; in aarch64_set_initial_registers_tid()
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dhazard-inlineasm.mir4 # the INLINEASM defs the vregs holding the data-to-be-stored by that preceding store,
Drename-disconnected-bug.ll2 ; Check that renameDisconnectedComponents() does not create vregs without a
/external/llvm/test/CodeGen/AMDGPU/
Drename-disconnected-bug.ll2 ; Check that renameDisconnectedComponents() does not create vregs without a
/external/swiftshader/third_party/llvm-7.0/llvm/docs/
DGlobalISel.rst91 registers. As opposed to non-generic vregs, they are not assigned a Register
92 Class. Instead, generic vregs have a :ref:`gmir-llt`, and can be assigned
96 non-generic vregs (e.g., use-def chains). Additionally, it also tracks the
100 For simplicity, most generic instructions only accept generic vregs:
198 and allow types on all vregs: this would reduce the number of MI required when
256 This differs from SelectionDAG's multiple vregs via ``GetValueVTs``.
261 information on vregs).
279 these vregs can have long live ranges.
298 * operating on **vregs that can be loaded and stored** -- if necessary, the
/external/kernel-headers/original/uapi/asm-arm64/asm/
Dsigcontext.h77 __uint128_t vregs[32]; member
Dptrace.h81 __uint128_t vregs[32]; member
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/WebAssembly/
Ddead-vreg.ll3 ; Check that unused vregs aren't assigned registers.
/external/llvm/test/CodeGen/WebAssembly/
Ddead-vreg.ll3 ; Check that unused vregs aren't assigned registers.
/external/google-breakpad/src/client/linux/dump_writer_common/
Dthread_info.cc226 my_memcpy(&out->float_save.regs, &fpregs.vregs,
Ducontext_reader.cc207 my_memcpy(&out->float_save.regs, &fpregs->vregs,
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dunused_stackslots.ll1 ; PR26374: Check no stack slots are allocated for vregs which have no real reference.
/external/llvm/test/CodeGen/X86/
Dunused_stackslots.ll1 ; PR26374: Check no stack slots are allocated for vregs which have no real reference.
/external/swiftshader/third_party/LLVM/test/Bindings/Ocaml/
Dvmcore.ml1194 (* Set up some vector vregs. *)
/external/llvm/test/Bindings/OCaml/
Dcore.ml1086 (* Set up some vector vregs. *)
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bindings/OCaml/
Dcore.ml1154 (* Set up some vector vregs. *)
/external/vixl/test/aarch64/
Dtest-trace-aarch64.cc2893 TEST(vregs) { TraceTestHelper(false, LOG_VREGS, REF("log-vregs")); } in TEST() argument