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Searched refs:vrsra (Results 1 – 25 of 27) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneont2-shiftaccum-encoding.s75 vrsra.s8 d5, d26, #8
76 vrsra.s16 d6, d25, #16
77 vrsra.s32 d7, d24, #32
78 vrsra.s64 d14, d23, #64
79 vrsra.u8 d15, d22, #8
80 vrsra.u16 d16, d21, #16
81 vrsra.u32 d17, d20, #32
82 vrsra.u64 d18, d19, #64
83 vrsra.s8 q1, q2, #8
84 vrsra.s16 q2, q3, #16
[all …]
Dneon-shiftaccum-encoding.s72 vrsra.s8 d5, d26, #8
73 vrsra.s16 d6, d25, #16
74 vrsra.s32 d7, d24, #32
75 vrsra.s64 d14, d23, #64
76 vrsra.u8 d15, d22, #8
77 vrsra.u16 d16, d21, #16
78 vrsra.u32 d17, d20, #32
79 vrsra.u64 d18, d19, #64
80 vrsra.s8 q1, q2, #8
81 vrsra.s16 q2, q3, #16
[all …]
/external/llvm/test/MC/ARM/
Dneont2-shiftaccum-encoding.s75 vrsra.s8 d5, d26, #8
76 vrsra.s16 d6, d25, #16
77 vrsra.s32 d7, d24, #32
78 vrsra.s64 d14, d23, #64
79 vrsra.u8 d15, d22, #8
80 vrsra.u16 d16, d21, #16
81 vrsra.u32 d17, d20, #32
82 vrsra.u64 d18, d19, #64
83 vrsra.s8 q1, q2, #8
84 vrsra.s16 q2, q3, #16
[all …]
Dneon-shiftaccum-encoding.s72 vrsra.s8 d5, d26, #8
73 vrsra.s16 d6, d25, #16
74 vrsra.s32 d7, d24, #32
75 vrsra.s64 d14, d23, #64
76 vrsra.u8 d15, d22, #8
77 vrsra.u16 d16, d21, #16
78 vrsra.u32 d17, d20, #32
79 vrsra.u64 d18, d19, #64
80 vrsra.s8 q1, q2, #8
81 vrsra.s16 q2, q3, #16
[all …]
/external/capstone/suite/MC/ARM/
Dneont2-shiftaccum-encoding.s.cs34 0x88,0xef,0x3a,0x53 = vrsra.s8 d5, d26, #8
35 0x90,0xef,0x39,0x63 = vrsra.s16 d6, d25, #16
36 0xa0,0xef,0x38,0x73 = vrsra.s32 d7, d24, #32
37 0x80,0xef,0xb7,0xe3 = vrsra.s64 d14, d23, #64
38 0x88,0xff,0x36,0xf3 = vrsra.u8 d15, d22, #8
39 0xd0,0xff,0x35,0x03 = vrsra.u16 d16, d21, #16
40 0xe0,0xff,0x34,0x13 = vrsra.u32 d17, d20, #32
41 0xc0,0xff,0xb3,0x23 = vrsra.u64 d18, d19, #64
42 0x88,0xef,0x54,0x23 = vrsra.s8 q1, q2, #8
43 0x90,0xef,0x56,0x43 = vrsra.s16 q2, q3, #16
[all …]
Dneon-shiftaccum-encoding.s.cs34 0x3a,0x53,0x88,0xf2 = vrsra.s8 d5, d26, #8
35 0x39,0x63,0x90,0xf2 = vrsra.s16 d6, d25, #16
36 0x38,0x73,0xa0,0xf2 = vrsra.s32 d7, d24, #32
37 0xb7,0xe3,0x80,0xf2 = vrsra.s64 d14, d23, #64
38 0x36,0xf3,0x88,0xf3 = vrsra.u8 d15, d22, #8
39 0x35,0x03,0xd0,0xf3 = vrsra.u16 d16, d21, #16
40 0x34,0x13,0xe0,0xf3 = vrsra.u32 d17, d20, #32
41 0xb3,0x23,0xc0,0xf3 = vrsra.u64 d18, d19, #64
42 0x54,0x23,0x88,0xf2 = vrsra.s8 q1, q2, #8
43 0x56,0x43,0x90,0xf2 = vrsra.s16 q2, q3, #16
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-shiftaccum-encoding.s37 @ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0xc8,0xef,0x30,0x13]
38 vrsra.s8 d17, d16, #8
39 @ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0xd0,0xef,0x30,0x13]
40 vrsra.s16 d17, d16, #16
41 @ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0xe0,0xef,0x30,0x13]
42 vrsra.s32 d17, d16, #32
43 @ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xc0,0xef,0xb0,0x13]
44 vrsra.s64 d17, d16, #64
45 @ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0xc8,0xff,0x30,0x13]
46 vrsra.u8 d17, d16, #8
[all …]
Dneon-shiftaccum-encoding.s35 @ CHECK: vrsra.s8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf2]
36 vrsra.s8 d17, d16, #8
37 @ CHECK: vrsra.s16 d17, d16, #16 @ encoding: [0x30,0x13,0xd0,0xf2]
38 vrsra.s16 d17, d16, #16
39 @ CHECK: vrsra.s32 d17, d16, #32 @ encoding: [0x30,0x13,0xe0,0xf2]
40 vrsra.s32 d17, d16, #32
41 @ CHECK: vrsra.s64 d17, d16, #64 @ encoding: [0xb0,0x13,0xc0,0xf2]
42 vrsra.s64 d17, d16, #64
43 @ CHECK: vrsra.u8 d17, d16, #8 @ encoding: [0x30,0x13,0xc8,0xf3]
44 vrsra.u8 d17, d16, #8
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvsra.ll165 ;CHECK: vrsra.s8
175 ;CHECK: vrsra.s16
185 ;CHECK: vrsra.s32
195 ;CHECK: vrsra.s64
205 ;CHECK: vrsra.u8
215 ;CHECK: vrsra.u16
225 ;CHECK: vrsra.u32
235 ;CHECK: vrsra.u64
245 ;CHECK: vrsra.s8
255 ;CHECK: vrsra.s16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvsra.ll165 ;CHECK: vrsra.s8
175 ;CHECK: vrsra.s16
185 ;CHECK: vrsra.s32
195 ;CHECK: vrsra.s64
205 ;CHECK: vrsra.u8
215 ;CHECK: vrsra.u16
225 ;CHECK: vrsra.u32
235 ;CHECK: vrsra.u64
245 ;CHECK: vrsra.s8
255 ;CHECK: vrsra.s16
[all …]
/external/llvm/test/CodeGen/ARM/
Dvsra.ll165 ;CHECK: vrsra.s8
175 ;CHECK: vrsra.s16
185 ;CHECK: vrsra.s32
195 ;CHECK: vrsra.s64
205 ;CHECK: vrsra.u8
215 ;CHECK: vrsra.u16
225 ;CHECK: vrsra.u32
235 ;CHECK: vrsra.u64
245 ;CHECK: vrsra.s8
255 ;CHECK: vrsra.s16
[all …]
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneont2.txt1210 # CHECK: vrsra.s8 d17, d16, #8
1212 # CHECK: vrsra.s16 d17, d16, #16
1214 # CHECK: vrsra.s32 d17, d16, #32
1216 # CHECK: vrsra.s64 d17, d16, #64
1218 # CHECK: vrsra.u8 d17, d16, #8
1220 # CHECK: vrsra.u16 d17, d16, #16
1222 # CHECK: vrsra.u32 d17, d16, #32
1224 # CHECK: vrsra.u64 d17, d16, #64
1226 # CHECK: vrsra.s8 q8, q9, #8
1228 # CHECK: vrsra.s16 q8, q9, #16
[all …]
Dneon.txt1401 # CHECK: vrsra.s8 d17, d16, #8
1403 # CHECK: vrsra.s16 d17, d16, #16
1405 # CHECK: vrsra.s32 d17, d16, #32
1407 # CHECK: vrsra.s64 d17, d16, #64
1409 # CHECK: vrsra.u8 d17, d16, #8
1411 # CHECK: vrsra.u16 d17, d16, #16
1413 # CHECK: vrsra.u32 d17, d16, #32
1415 # CHECK: vrsra.u64 d17, d16, #64
1417 # CHECK: vrsra.s8 q8, q9, #8
1419 # CHECK: vrsra.s16 q8, q9, #16
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1210 # CHECK: vrsra.s8 d17, d16, #8
1212 # CHECK: vrsra.s16 d17, d16, #16
1214 # CHECK: vrsra.s32 d17, d16, #32
1216 # CHECK: vrsra.s64 d17, d16, #64
1218 # CHECK: vrsra.u8 d17, d16, #8
1220 # CHECK: vrsra.u16 d17, d16, #16
1222 # CHECK: vrsra.u32 d17, d16, #32
1224 # CHECK: vrsra.u64 d17, d16, #64
1226 # CHECK: vrsra.s8 q8, q9, #8
1228 # CHECK: vrsra.s16 q8, q9, #16
[all …]
Dneon.txt1401 # CHECK: vrsra.s8 d17, d16, #8
1403 # CHECK: vrsra.s16 d17, d16, #16
1405 # CHECK: vrsra.s32 d17, d16, #32
1407 # CHECK: vrsra.s64 d17, d16, #64
1409 # CHECK: vrsra.u8 d17, d16, #8
1411 # CHECK: vrsra.u16 d17, d16, #16
1413 # CHECK: vrsra.u32 d17, d16, #32
1415 # CHECK: vrsra.u64 d17, d16, #64
1417 # CHECK: vrsra.s8 q8, q9, #8
1419 # CHECK: vrsra.s16 q8, q9, #16
[all …]
/external/llvm/test/MC/Disassembler/ARM/
Dneont2.txt1210 # CHECK: vrsra.s8 d17, d16, #8
1212 # CHECK: vrsra.s16 d17, d16, #16
1214 # CHECK: vrsra.s32 d17, d16, #32
1216 # CHECK: vrsra.s64 d17, d16, #64
1218 # CHECK: vrsra.u8 d17, d16, #8
1220 # CHECK: vrsra.u16 d17, d16, #16
1222 # CHECK: vrsra.u32 d17, d16, #32
1224 # CHECK: vrsra.u64 d17, d16, #64
1226 # CHECK: vrsra.s8 q8, q9, #8
1228 # CHECK: vrsra.s16 q8, q9, #16
[all …]
Dneon.txt1401 # CHECK: vrsra.s8 d17, d16, #8
1403 # CHECK: vrsra.s16 d17, d16, #16
1405 # CHECK: vrsra.s32 d17, d16, #32
1407 # CHECK: vrsra.s64 d17, d16, #64
1409 # CHECK: vrsra.u8 d17, d16, #8
1411 # CHECK: vrsra.u16 d17, d16, #16
1413 # CHECK: vrsra.u32 d17, d16, #32
1415 # CHECK: vrsra.u64 d17, d16, #64
1417 # CHECK: vrsra.s8 q8, q9, #8
1419 # CHECK: vrsra.s16 q8, q9, #16
[all …]
/external/arm-neon-tests/
Dref_vrsra_n.c40 vrsra##Q##_n_##T2##W(VECT_VAR(vector, T1, W, N), \ in exec_vrsra_n()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7786 "vrsqrte\007vrsqrts\005vrsra\007vrsubhn\005vsdot\006vseleq\006vselge\006"
11117 …{ 2530 /* vrsra */, ARM::VRSRAsv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,…
11118 …{ 2530 /* vrsra */, ARM::VRSRAsv4i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,…
11119 …{ 2530 /* vrsra */, ARM::VRSRAsv4i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,…
11120 …{ 2530 /* vrsra */, ARM::VRSRAsv2i32, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm321_3__CondCode2_0,…
11121 …{ 2530 /* vrsra */, ARM::VRSRAsv2i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,…
11122 …{ 2530 /* vrsra */, ARM::VRSRAsv1i64, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm641_3__CondCode2_0,…
11123 …{ 2530 /* vrsra */, ARM::VRSRAsv16i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, …
11124 …{ 2530 /* vrsra */, ARM::VRSRAsv8i8, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm81_3__CondCode2_0, F…
11125 …{ 2530 /* vrsra */, ARM::VRSRAuv8i16, Convert__Reg1_2__Tie0_1_1__Reg1_2__ShrImm161_3__CondCode2_0,…
[all …]
/external/vixl/src/aarch32/
Dassembler-aarch32.h5673 void vrsra(Condition cond,
5678 void vrsra(DataType dt, DRegister rd, DRegister rm, const DOperand& operand) { in vrsra() function
5679 vrsra(al, dt, rd, rm, operand); in vrsra()
5682 void vrsra(Condition cond,
5687 void vrsra(DataType dt, QRegister rd, QRegister rm, const QOperand& operand) { in vrsra() function
5688 vrsra(al, dt, rd, rm, operand); in vrsra()
Ddisasm-aarch32.h2395 void vrsra(Condition cond,
2401 void vrsra(Condition cond,
Ddisasm-aarch32.cc6391 void Disassembler::vrsra(Condition cond, in vrsra() function in vixl::aarch32::Disassembler
6405 void Disassembler::vrsra(Condition cond, in vrsra() function in vixl::aarch32::Disassembler
31281 vrsra(CurrentCond(), in DecodeT32()
36439 vrsra(CurrentCond(), in DecodeT32()
43897 vrsra(al, dt, DRegister(rd), DRegister(rm), imm); in DecodeA32()
48035 vrsra(al, dt, QRegister(rd), QRegister(rm), imm); in DecodeA32()
Dassembler-aarch32.cc25069 void Assembler::vrsra(Condition cond, in vrsra() function in vixl::aarch32::Assembler
25108 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand); in vrsra()
25111 void Assembler::vrsra(Condition cond, in vrsra() function in vixl::aarch32::Assembler
25150 Delegate(kVrsra, &Assembler::vrsra, cond, dt, rd, rm, operand); in vrsra()
Dmacro-assembler-aarch32.h9549 vrsra(cond, dt, rd, rm, operand); in Vrsra()
9567 vrsra(cond, dt, rd, rm, operand); in Vrsra()
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td4210 defm VRSRAs : N2VShAdd_QHSD<0, 1, 0b0011, 1, "vrsra", "s", NEONvrshrs>;
4211 defm VRSRAu : N2VShAdd_QHSD<1, 1, 0b0011, 1, "vrsra", "u", NEONvrshru>;

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