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/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-sub-encoding.s103 @ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3]
104 vrsubhn.i16 d16, q8, q9
105 @ CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3]
106 vrsubhn.i32 d16, q8, q9
107 @ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
108 vrsubhn.i64 d16, q8, q9
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvsub.ll126 ;CHECK: vrsubhn.i16
129 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
135 ;CHECK: vrsubhn.i32
138 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
144 ;CHECK: vrsubhn.i64
147 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
151 declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
152 declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
153 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvsub.ll122 ;CHECK: vrsubhn.i16
125 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
131 ;CHECK: vrsubhn.i32
134 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
140 ;CHECK: vrsubhn.i64
143 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
147 declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
148 declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
149 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
/external/llvm/test/CodeGen/ARM/
Dvsub.ll122 ;CHECK: vrsubhn.i16
125 %tmp3 = call <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16> %tmp1, <8 x i16> %tmp2)
131 ;CHECK: vrsubhn.i32
134 %tmp3 = call <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32> %tmp1, <4 x i32> %tmp2)
140 ;CHECK: vrsubhn.i64
143 %tmp3 = call <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64> %tmp1, <2 x i64> %tmp2)
147 declare <8 x i8> @llvm.arm.neon.vrsubhn.v8i8(<8 x i16>, <8 x i16>) nounwind readnone
148 declare <4 x i16> @llvm.arm.neon.vrsubhn.v4i16(<4 x i32>, <4 x i32>) nounwind readnone
149 declare <2 x i32> @llvm.arm.neon.vrsubhn.v2i32(<2 x i64>, <2 x i64>) nounwind readnone
/external/llvm/test/MC/ARM/
Dneon-sub-encoding.s129 @ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3]
130 vrsubhn.i16 d16, q8, q9
131 @ CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3]
132 vrsubhn.i32 d16, q8, q9
133 @ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
134 vrsubhn.i64 d16, q8, q9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-sub-encoding.s129 @ CHECK: vrsubhn.i16 d16, q8, q9 @ encoding: [0xa2,0x06,0xc0,0xf3]
130 vrsubhn.i16 d16, q8, q9
131 @ CHECK: vrsubhn.i32 d16, q8, q9 @ encoding: [0xa2,0x06,0xd0,0xf3]
132 vrsubhn.i32 d16, q8, q9
133 @ CHECK: vrsubhn.i64 d16, q8, q9 @ encoding: [0xa2,0x06,0xe0,0xf3]
134 vrsubhn.i64 d16, q8, q9
/external/capstone/suite/MC/ARM/
Dneon-sub-encoding.s.cs62 0xa2,0x06,0xc0,0xf3 = vrsubhn.i16 d16, q8, q9
63 0xa2,0x06,0xd0,0xf3 = vrsubhn.i32 d16, q8, q9
64 0xa2,0x06,0xe0,0xf3 = vrsubhn.i64 d16, q8, q9
/external/arm-neon-tests/
Dref_vrsubhn.c26 #define INSN_NAME vrsubhn
DMakefile.gcc57 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
DMakefile51 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll109 define <8 x i16> @vrsubhn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind read…
110 ; CHECK-LABEL: vrsubhn:
/external/llvm/test/CodeGen/AArch64/
Darm64-vecFold.ll109 define <8 x i16> @vrsubhn(<8 x i16> %a0, <8 x i16> %a1, <8 x i16> %b0, <8 x i16> %b1) nounwind read…
110 ; CHECK-LABEL: vrsubhn:
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt1613 # CHECK: vrsubhn.i16 d16, q8, q9
1615 # CHECK: vrsubhn.i32 d16, q8, q9
1617 # CHECK: vrsubhn.i64 d16, q8, q9
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/ARM/
Dneon.txt1613 # CHECK: vrsubhn.i16 d16, q8, q9
1615 # CHECK: vrsubhn.i32 d16, q8, q9
1617 # CHECK: vrsubhn.i64 d16, q8, q9
/external/llvm/test/MC/Disassembler/ARM/
Dneon.txt1613 # CHECK: vrsubhn.i16 d16, q8, q9
1615 # CHECK: vrsubhn.i32 d16, q8, q9
1617 # CHECK: vrsubhn.i64 d16, q8, q9
/external/clang/include/clang/Basic/
Darm_neon.td431 def OP_RSUBHNHi : Op<(call "vcombine", $p0, (call "vrsubhn", $p1, $p2))>;
547 def VRSUBHN : IInst<"vrsubhn", "hkk", "silUsUiUl">;
/external/vixl/src/aarch32/
Dassembler-aarch32.h5691 void vrsubhn(
5693 void vrsubhn(DataType dt, DRegister rd, QRegister rn, QRegister rm) { in vrsubhn() function
5694 vrsubhn(al, dt, rd, rn, rm); in vrsubhn()
Ddisasm-aarch32.h2407 void vrsubhn(
Ddisasm-aarch32.cc6419 void Disassembler::vrsubhn( in vrsubhn() function in vixl::aarch32::Disassembler
28865 vrsubhn(CurrentCond(), in DecodeT32()
43013 vrsubhn(al, in DecodeA32()
Dassembler-aarch32.cc25153 void Assembler::vrsubhn( in vrsubhn() function in vixl::aarch32::Assembler
25178 Delegate(kVrsubhn, &Assembler::vrsubhn, cond, dt, rd, rn, rm); in vrsubhn()
Dmacro-assembler-aarch32.h9582 vrsubhn(cond, dt, rd, rn, rm); in Vrsubhn()
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenAsmMatcher.inc7786 "vrsqrte\007vrsqrts\005vrsra\007vrsubhn\005vsdot\006vseleq\006vselge\006"
11149 …{ 2536 /* vrsubhn */, ARM::VRSUBHNv8i8, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_HasN…
11150 …{ 2536 /* vrsubhn */, ARM::VRSUBHNv4i16, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Has…
11151 …{ 2536 /* vrsubhn */, ARM::VRSUBHNv2i32, Convert__Reg1_2__Reg1_3__Reg1_4__CondCode2_0, Feature_Has…
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td3657 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td4699 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td4973 defm VRSUBHN : N3VNInt_HSD<1,1,0b0110,0, "vrsubhn", "i",

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