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Searched refs:vs_inputs (Results 1 – 6 of 6) sorted by relevance

/external/mesa3d/src/mesa/drivers/dri/i965/
Dbrw_draw_upload.c461 GLbitfield64 vs_inputs = vs_prog_data->inputs_read; in brw_prepare_vertices() local
481 vs_inputs |= VERT_BIT_EDGEFLAG; in brw_prepare_vertices()
489 while (vs_inputs) { in brw_prepare_vertices()
490 GLuint first = ffsll(vs_inputs) - 1; in brw_prepare_vertices()
497 vs_inputs &= ~BITFIELD64_BIT(first); in brw_prepare_vertices()
499 vs_inputs &= ~BITFIELD64_BIT(first + 1); in brw_prepare_vertices()
/external/mesa3d/src/intel/blorp/
Dblorp_priv.h198 struct blorp_vs_inputs vs_inputs; member
Dblorp_genX_exec.h240 assert(sizeof(params->vs_inputs) == 16); in blorp_emit_input_varying_data()
241 memcpy(inputs, &params->vs_inputs, sizeof(params->vs_inputs)); in blorp_emit_input_varying_data()
Dblorp_clear.c713 params.vs_inputs.base_layer = start_layer; in blorp_clear_attachments()
/external/virglrenderer/src/gallium/auxiliary/tgsi/
Dtgsi_ureg.c109 unsigned vs_inputs[UREG_MAX_INPUT/32]; member
316 ureg->vs_inputs[index/32] |= 1 << (index % 32); in ureg_DECL_vs_input()
1350 if (ureg->vs_inputs[i/32] & (1 << (i%32))) { in emit_decls()
/external/mesa3d/src/gallium/auxiliary/tgsi/
Dtgsi_ureg.c127 unsigned vs_inputs[PIPE_MAX_ATTRIBS/32]; member
356 assert(index / 32 < ARRAY_SIZE(ureg->vs_inputs)); in ureg_DECL_vs_input()
358 ureg->vs_inputs[index/32] |= 1 << (index % 32); in ureg_DECL_vs_input()
1821 if (ureg->vs_inputs[i/32] & (1u << (i%32))) { in emit_decls()