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/external/libavc/encoder/arm/
Dih264e_half_pel.s355 …vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding…
357 …vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
373 …vshrn.s32 d28, q1, #8 @// shift by 8 and later we will shift by 2 more with rounding…
380 …vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
402 …vshrn.s32 d28, q11, #8 @// shift by 8 and later we will shift by 2 more with rounding…
460 …vshrn.s32 d21, q10, #8 @// shift by 8 and later we will shift by 2 more with rounding…
462 …vshrn.s32 d20, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
478 …vshrn.s32 d28, q3, #8 @// shift by 8 and later we will shift by 2 more with rounding…
485 …vshrn.s32 d29, q13, #8 @// shift by 8 and later we will shift by 2 more with rounding…
507 …vshrn.s32 d28, q11, #8 @// shift by 8 and later we will shift by 2 more with rounding…
[all …]
/external/libjpeg-turbo/simd/arm/
Djsimd_neon.S429 vshrn.s32 ROW1L, q1, #16
437 vshrn.s32 ROW2R, q1, #16 /* ROW6L <-> ROW2R */
441 vshrn.s32 ROW2L, q1, #16
442 vshrn.s32 ROW1R, q3, #16 /* ROW5L <-> ROW1R */
451 vshrn.s32 ROW3R, q2, #16 /* ROW7L <-> ROW3R */
452 vshrn.s32 ROW3L, q5, #16
453 vshrn.s32 ROW0L, q6, #16
454 vshrn.s32 ROW0R, q3, #16 /* ROW4L <-> ROW0R */
478 vshrn.s32 ROW5L, q1, #16 /* ROW5L <-> ROW1R */
486 vshrn.s32 ROW6R, q1, #16
[all …]
/external/libhevc/common/arm/
Dihevc_inter_pred_luma_vert_w16inp_w16out.s207 vshrn.s32 d8, q4, #6
226 vshrn.s32 d10, q5, #6
251 vshrn.s32 d12, q6, #6
269 vshrn.s32 d14, q7, #6
296 vshrn.s32 d8, q4, #6
317 vshrn.s32 d10, q5, #6
338 vshrn.s32 d12, q6, #6
353 vshrn.s32 d14, q7, #6
367 vshrn.s32 d8, q4, #6
380 vshrn.s32 d10, q5, #6
[all …]
Dihevc_intra_pred_filters_chroma_mode_19_to_25.s263 vshrn.s16 d5,q1,#5 @idx = pos >> 5
392 vshrn.s16 d3,q1,#5 @idx = pos >> 5
492 vshrn.s16 d3,q1,#5 @idx = pos >> 5
Dihevc_intra_pred_chroma_mode_27_to_33.s153 vshrn.u16 d5,q1,#5 @idx = pos >> 5
284 vshrn.u16 d3,q1,#5 @idx = pos >> 5
380 vshrn.u16 d3,q1,#5 @idx = pos >> 5
Dihevc_intra_pred_luma_mode_27_to_33.s156 vshrn.u16 d5,q1,#5 @idx = pos >> 5
285 vshrn.u16 d3,q1,#5 @idx = pos >> 5
380 vshrn.u16 d3,q1,#5 @idx = pos >> 5
Dihevc_intra_pred_filters_luma_mode_19_to_25.s268 vshrn.s16 d5,q1,#5 @idx = pos >> 5
391 vshrn.s16 d3,q1,#5 @idx = pos >> 5
488 vshrn.s16 d3,q1,#5 @idx = pos >> 5
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneont2-shift-encoding.s87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
Dneon-shift-encoding.s273 vshrn.i16 d16, q8, #8
274 vshrn.i32 d16, q8, #16
275 vshrn.i64 d16, q8, #32
277 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
278 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
279 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
/external/llvm/test/MC/ARM/
Dneont2-shift-encoding.s87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
Dneon-shift-encoding.s273 vshrn.i16 d16, q8, #8
274 vshrn.i32 d16, q8, #16
275 vshrn.i64 d16, q8, #32
277 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
278 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
279 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneont2-shift-encoding.s87 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0xc8,0xef,0x30,0x08]
88 vshrn.i16 d16, q8, #8
89 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0xd0,0xef,0x30,0x08]
90 vshrn.i32 d16, q8, #16
91 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0xe0,0xef,0x30,0x08]
92 vshrn.i64 d16, q8, #32
Dneon-shift-encoding.s150 @ CHECK: vshrn.i16 d16, q8, #8 @ encoding: [0x30,0x08,0xc8,0xf2]
151 vshrn.i16 d16, q8, #8
152 @ CHECK: vshrn.i32 d16, q8, #16 @ encoding: [0x30,0x08,0xd0,0xf2]
153 vshrn.i32 d16, q8, #16
154 @ CHECK: vshrn.i64 d16, q8, #32 @ encoding: [0x30,0x08,0xe0,0xf2]
155 vshrn.i64 d16, q8, #32
/external/capstone/suite/MC/ARM/
Dneont2-shift-encoding.s.cs43 0xc8,0xef,0x30,0x08 = vshrn.i16 d16, q8, #8
44 0xd0,0xef,0x30,0x08 = vshrn.i32 d16, q8, #16
45 0xe0,0xef,0x30,0x08 = vshrn.i64 d16, q8, #32
Dneon-shift-encoding.s.cs123 0x30,0x08,0xc8,0xf2 = vshrn.i16 d16, q8, #8
124 0x30,0x08,0xd0,0xf2 = vshrn.i32 d16, q8, #16
125 0x30,0x08,0xe0,0xf2 = vshrn.i64 d16, q8, #32
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvshrn.ll5 ;CHECK: vshrn.i16
13 ;CHECK: vshrn.i32
21 ;CHECK: vshrn.i64
Dreg_sequence.ll18 ; CHECK: vshrn.i32
19 ; CHECK: vshrn.i32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvshrn.ll5 ;CHECK: vshrn.i16
14 ;CHECK: vshrn.i32
23 ;CHECK: vshrn.i64
Dreg_sequence.ll18 ; CHECK: vshrn.i32
19 ; CHECK: vshrn.i32
/external/llvm/test/CodeGen/ARM/
Dvshrn.ll5 ;CHECK: vshrn.i16
14 ;CHECK: vshrn.i32
23 ;CHECK: vshrn.i64
Dreg_sequence.ll18 ; CHECK: vshrn.i32
19 ; CHECK: vshrn.i32
/external/libavc/common/arm/
Dih264_resi_trans_quant_a9.s519 vshrn.s32 d0, q0, #1 @i4_value = (x0 + x1) >> 1;
520 vshrn.s32 d1, q1, #1 @i4_value = (x3 + x2) >> 1;
521 vshrn.s32 d2, q2, #1 @i4_value = (x0 - x1) >> 1;
522 vshrn.s32 d3, q3, #1 @i4_value = (x3 - x2) >> 1;
562 vshrn.u16 d14, q5, #8
563 vshrn.u16 d15, q6, #8
675 vshrn.u16 d14, q7, #8 @reduce nnz comparison to 1 bit
/external/boringssl/src/crypto/poly1305/
Dpoly1305_arm_asm.S712 # asm 1: vshrn.u64 <v23=reg128#10%top,<d23=reg128#2,#14
713 # asm 2: vshrn.u64 <v23=d19,<d23=q1,#14
714 vshrn.u64 d19,q1,#14
724 # asm 1: vshrn.u64 <v01=reg128#11%top,<d01=reg128#12,#26
725 # asm 2: vshrn.u64 <v01=d21,<d01=q11,#26
726 vshrn.u64 d21,q11,#26
744 # asm 1: vshrn.u64 <v23=reg128#10%bot,<mid=reg128#1,#20
745 # asm 2: vshrn.u64 <v23=d18,<mid=q0,#20
746 vshrn.u64 d18,q0,#20
/external/libvpx/libvpx/vpx_dsp/arm/
Dloopfilter_8_neon.asm299 vshrn.u16 d30, q10, #4
/external/libvpx/config/arm-neon/vpx_dsp/arm/
Dloopfilter_8_neon.asm.S313 vshrn.u16 d30, q10, #4

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