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Searched refs:vsubw (Results 1 – 25 of 51) sorted by relevance

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/external/llvm/test/MC/ARM/
Dneon-sub-encoding.s61 @ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
62 vsubw.s8 q8, q8, d18
63 @ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
64 vsubw.s16 q8, q8, d18
65 @ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
66 vsubw.s32 q8, q8, d18
67 @ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
68 vsubw.u8 q8, q8, d18
69 @ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
70 vsubw.u16 q8, q8, d18
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/
Dneon-sub-encoding.s61 @ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
62 vsubw.s8 q8, q8, d18
63 @ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
64 vsubw.s16 q8, q8, d18
65 @ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
66 vsubw.s32 q8, q8, d18
67 @ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
68 vsubw.u8 q8, q8, d18
69 @ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
70 vsubw.u16 q8, q8, d18
[all …]
/external/capstone/suite/MC/ARM/
Dneon-sub-encoding.s.cs28 0xa2,0x03,0xc0,0xf2 = vsubw.s8 q8, q8, d18
29 0xa2,0x03,0xd0,0xf2 = vsubw.s16 q8, q8, d18
30 0xa2,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d18
31 0xa2,0x03,0xc0,0xf3 = vsubw.u8 q8, q8, d18
32 0xa2,0x03,0xd0,0xf3 = vsubw.u16 q8, q8, d18
33 0xa2,0x03,0xe0,0xf3 = vsubw.u32 q8, q8, d18
77 0x05,0xc3,0x8c,0xf2 = vsubw.s8 q6, q6, d5
78 0x01,0xe3,0x9e,0xf2 = vsubw.s16 q7, q7, d1
79 0x82,0x03,0xe0,0xf2 = vsubw.s32 q8, q8, d2
80 0x05,0xc3,0x8c,0xf3 = vsubw.u8 q6, q6, d5
[all …]
/external/swiftshader/third_party/LLVM/test/MC/ARM/
Dneon-sub-encoding.s35 @ CHECK: vsubw.s8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf2]
36 vsubw.s8 q8, q8, d18
37 @ CHECK: vsubw.s16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf2]
38 vsubw.s16 q8, q8, d18
39 @ CHECK: vsubw.s32 q8, q8, d18 @ encoding: [0xa2,0x03,0xe0,0xf2]
40 vsubw.s32 q8, q8, d18
41 @ CHECK: vsubw.u8 q8, q8, d18 @ encoding: [0xa2,0x03,0xc0,0xf3]
42 vsubw.u8 q8, q8, d18
43 @ CHECK: vsubw.u16 q8, q8, d18 @ encoding: [0xa2,0x03,0xd0,0xf3]
44 vsubw.u16 q8, q8, d18
[all …]
/external/libavc/common/arm/
Dih264_iquant_itrans_recon_a9.s631 vsubw.s16 q12, q12, d6 @ y3 (0-3) 1+7-3
632 vsubw.s16 q13, q13, d7 @ y3 (0-7) 1+7-3
641 vsubw.s16 q12, q12, d12 @
642 vsubw.s16 q13, q13, d13 @
667 vsubw.s16 q10, q10, d14 @
668 vsubw.s16 q11, q11, d15 @
675 vsubw.s16 q10, q10, d14 @
676 vsubw.s16 q11, q11, d15 @
753 vsubw.s16 q12, q12, d6 @
754 vsubw.s16 q13, q13, d7 @
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/ARM/
Dvsub.ll223 ;CHECK: vsubw.s8
233 ;CHECK: vsubw.s16
243 ;CHECK: vsubw.s32
253 ;CHECK: vsubw.u8
263 ;CHECK: vsubw.u16
273 ;CHECK: vsubw.u32
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/
Dvsub.ll219 ;CHECK: vsubw.s8
229 ;CHECK: vsubw.s16
239 ;CHECK: vsubw.s32
249 ;CHECK: vsubw.u8
259 ;CHECK: vsubw.u16
269 ;CHECK: vsubw.u32
/external/llvm/test/CodeGen/ARM/
Dvsub.ll219 ;CHECK: vsubw.s8
229 ;CHECK: vsubw.s16
239 ;CHECK: vsubw.s32
249 ;CHECK: vsubw.u8
259 ;CHECK: vsubw.u16
269 ;CHECK: vsubw.u32
/external/arm-neon-tests/
Dref_vsubw.c26 #define INSN_NAME vsubw
DMakefile.gcc57 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
DMakefile51 vhadd vrhadd vhsub vsubl vsubw vsubhn vrsubhn vmvn vqmovn \
/external/llvm/test/CodeGen/Hexagon/vect/
Dvect-vsubw.ll2 ; CHECK: vsubw
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/vect/
Dvect-vsubw.ll2 ; CHECK: vsubw
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/
Dv6vec-vmemu1.ll16 %v2 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
57 declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
Dv6vec_inc1.ll23 %v2 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
64 declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
Dv60-vecpred-spill.ll14 %v3 = tail call <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32> undef, <16 x i32> undef)
145 declare <16 x i32> @llvm.hexagon.V6.vsubw(<16 x i32>, <16 x i32>) #1
/external/libvpx/libvpx/vpx_dsp/arm/
Dloopfilter_16_neon.asm528 vsubw.u8 q15, d4 ; oq0 = op0 - p3
529 vsubw.u8 q15, d7 ; oq0 -= p0
534 vsubw.u8 q15, d5 ; oq1 = oq0 - p2
535 vsubw.u8 q15, d8 ; oq1 -= q0
540 vsubw.u8 q15, d6 ; oq2 = oq0 - p1
541 vsubw.u8 q15, d9 ; oq2 -= q1
/external/libvpx/config/arm-neon/vpx_dsp/arm/
Dloopfilter_16_neon.asm.S544 vsubw.u8 q15, d4 @ oq0 = op0 - p3
545 vsubw.u8 q15, d7 @ oq0 -= p0
550 vsubw.u8 q15, d5 @ oq1 = oq0 - p2
551 vsubw.u8 q15, d8 @ oq1 -= q0
556 vsubw.u8 q15, d6 @ oq2 = oq0 - p1
557 vsubw.u8 q15, d9 @ oq2 -= q1
/external/libhevc/common/arm/
Dihevc_deblk_chroma_vert.s120 vsubw.u8 q2,q0,d4
Dihevc_deblk_luma_horz.s480 vsubw.s8 q2,q3,d8
533 vsubw.s8 q7,q7,d8
/external/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt393 # CHECK: r17:16 = vsubw(r21:20, r31:30)
395 # CHECK: r17:16 = vsubw(r21:20, r31:30):sat
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/Hexagon/
Dxtype_alu.txt393 # CHECK: r17:16 = vsubw(r21:20,r31:30)
395 # CHECK: r17:16 = vsubw(r21:20,r31:30):sat
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll1012 declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
1014 %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
1017 ; CHECK: = vsubw({{.*}},{{.*}})
1024 ; CHECK: = vsubw({{.*}},{{.*}}):sat
/external/llvm/test/CodeGen/Hexagon/intrinsics/
Dxtype_alu.ll1012 declare i64 @llvm.hexagon.A2.vsubw(i64, i64)
1014 %z = call i64 @llvm.hexagon.A2.vsubw(i64 %a, i64 %b)
1017 ; CHECK: = vsubw({{.*}}, {{.*}})
1024 ; CHECK: = vsubw({{.*}}, {{.*}}):sat
/external/swiftshader/third_party/LLVM/test/MC/Disassembler/ARM/
Dneon.txt1545 # CHECK: vsubw.s8 q8, q8, d18
1547 # CHECK: vsubw.s16 q8, q8, d18
1549 # CHECK: vsubw.s32 q8, q8, d18
1551 # CHECK: vsubw.u8 q8, q8, d18
1553 # CHECK: vsubw.u16 q8, q8, d18
1555 # CHECK: vsubw.u32 q8, q8, d18

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