| /external/llvm/test/MC/ARM/ |
| D | neon-vswp.s | 3 vswp d1, d2 define
4 vswp q1, q2 label
6 @ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
7 @ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | neon-vswp.s | 3 vswp d1, d2 define
4 vswp q1, q2 label
6 @ CHECK: vswp d1, d2 @ encoding: [0x02,0x10,0xb2,0xf3]
7 @ CHECK: vswp q1, q2 @ encoding: [0x44,0x20,0xb2,0xf3]
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-vswp.s.cs | 2 0x02,0x10,0xb2,0xf3 = vswp d1, d2
3 0x44,0x20,0xb2,0xf3 = vswp q1, q2
|
| /external/libavc/common/arm/ |
| D | ih264_iquant_itrans_recon_a9.s | 179 vswp d6, d7 @Reverse positions of x2 and x3 define
186 vswp d12, d13
204 vswp d16, d17 @Reverse positions of x2 and x3
209 vswp d22, d23
353 vswp d6, d7 @Reverse positions of x2 and x3 define
361 vswp d12, d13
379 vswp d16, d17 @Reverse positions of x2 and x3
385 vswp d22, d23
601 vswp d1, d8 @ Q0/Q1 = Row order x0/x1 define
602 vswp d3, d10 @ Q2/Q3 = Row order x2/x3 define
[all …]
|
| D | ih264_ihadamard_scaling_a9.s | 126 vswp d5, d8 @Q2 = x4, Q4 = x6 define
127 vswp d7, d10 @Q3 = x5, Q5 = x7 define
|
| D | ih264_resi_trans_quant_a9.s | 500 vswp d15, d18
501 vswp d17, d20
|
| /external/libxaac/decoder/armv7/ |
| D | ixheaacd_esbr_fwd_modulation.s | 45 vswp d4, d7 define
46 vswp d5, d6 define
|
| /external/libhevc/common/arm/ |
| D | ihevc_itrans_recon_8x8.s | 534 vswp d3,d6 define
537 vswp d5,d8 define
768 vswp d3,d6 define
771 vswp d5,d8 define
858 vswp d11,d14
859 vswp d13,d16
|
| D | ihevc_itrans_recon_16x16.s | 1071 vswp d5,d18 define
1072 vswp d23,d14
1073 vswp d13,d20
1074 vswp d31,d8
|
| D | ihevc_itrans_recon_32x32.s | 2758 vswp d13,d16
2759 vswp d21,d24
2760 vswp d15,d18
2761 vswp d23,d26
2823 vswp d13,d16
2824 vswp d21,d24
2825 vswp d15,d18
2826 vswp d23,d26
|
| /external/libmpeg2/common/arm/ |
| D | impeg2_idct.s | 802 vswp d3, d6 define
805 vswp d5, d8 define
1040 vswp d3, d6 define
1043 vswp d5, d8 define
1130 vswp d11, d14
1131 vswp d13, d16
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | idct4x4_add_neon.asm | 103 vswp d18, d19
|
| D | loopfilter_16_neon.asm | 219 vswp d23, d25
|
| /external/libvpx/config/arm-neon/vpx_dsp/arm/ |
| D | idct4x4_add_neon.asm.S | 111 vswp d18, d19
|
| D | loopfilter_16_neon.asm.S | 232 vswp d23, d25
|
| /external/libjpeg-turbo/simd/arm/ |
| D | jsimd_neon.S | 803 vswp d28, d21
804 vswp d26, d19
807 vswp d30, d23
809 vswp d24, d17
2050 vswp d30, d23
2051 vswp d24, d17
2052 vswp d26, d19
2055 vswp d28, d21
|
| /external/vixl/src/aarch32/ |
| D | assembler-aarch32.h | 6067 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
6068 void vswp(DataType dt, DRegister rd, DRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6069 void vswp(DRegister rd, DRegister rm) { in vswp() function
6070 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
6072 void vswp(Condition cond, DRegister rd, DRegister rm) { in vswp() function
6073 vswp(cond, kDataTypeValueNone, rd, rm); in vswp()
6076 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
6077 void vswp(DataType dt, QRegister rd, QRegister rm) { vswp(al, dt, rd, rm); } in vswp() function
6078 void vswp(QRegister rd, QRegister rm) { in vswp() function
6079 vswp(al, kDataTypeValueNone, rd, rm); in vswp()
[all …]
|
| D | disasm-aarch32.h | 2591 void vswp(Condition cond, DataType dt, DRegister rd, DRegister rm);
2593 void vswp(Condition cond, DataType dt, QRegister rd, QRegister rm);
|
| /external/v8/src/arm/ |
| D | assembler-arm.h | 1256 void vswp(DwVfpRegister dst, DwVfpRegister src);
1257 void vswp(QwNeonRegister dst, QwNeonRegister src);
|
| D | macro-assembler-arm.cc | 397 vswp(srcdst0, srcdst1); in Swap()
409 vswp(srcdst0, srcdst1); in Swap()
|
| D | assembler-arm.cc | 4149 void Assembler::vswp(DwVfpRegister dst, DwVfpRegister src) { in vswp() function in v8::internal::Assembler
4157 void Assembler::vswp(QwNeonRegister dst, QwNeonRegister src) { in vswp() function in v8::internal::Assembler
|
| /external/boringssl/src/crypto/poly1305/ |
| D | poly1305_arm_asm.S | 683 # asm 1: vswp <d23=reg128#2%bot,<d01=reg128#12%top
684 # asm 2: vswp <d23=d2,<d01=d23
685 vswp d2,d23 define
|
| /external/libavc/encoder/arm/ |
| D | ime_distortion_metrics_a9q.s | 1045 vswp d10, d11 @I rearrange so that the q4 and q5 add properly
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenAsmMatcher.inc | 1111 Mnemonic = "vswp";
7789 "r\004vsub\006vsubhn\005vsubl\005vsubw\004vswp\004vtbl\004vtbx\004vtrn\004"
11586 …{ 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_H…
11587 …{ 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_1__Reg1_2__Tie0_1_1__Tie1_1_1__CondCode2_0, Feature_H…
11588 …{ 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
11589 …{ 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
11590 …{ 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
11591 …{ 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
11592 …{ 2684 /* vswp */, ARM::VSWPq, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
11593 …{ 2684 /* vswp */, ARM::VSWPd, Convert__Reg1_2__Reg1_3__Tie0_3_3__Tie1_4_4__CondCode2_0, Feature_H…
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrNEON.td | 5675 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
5679 NoItinerary, "vswp", "$Vd, $Vm", "$in1 = $Vd, $in2 = $Vm",
8105 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8107 defm : NEONDTAnyInstAlias<"vswp${p}", "$Vd, $Vm",
8169 def : NEONMnemonicAlias<"vswpq", "vswp">;
|