| /external/boringssl/ios-aarch64/crypto/test/ |
| D | trampoline-armv8.S | 115 str xzr, [x1]
137 mov x0, xzr
145 mov x1, xzr
153 mov x2, xzr
161 mov x3, xzr
169 mov x4, xzr
177 mov x5, xzr
185 mov x6, xzr
193 mov x7, xzr
201 mov x8, xzr
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | reg-scavenge-frame.mir | 16 $x0 = COPY $xzr
17 $x1 = COPY $xzr
18 $x2 = COPY $xzr
19 $x3 = COPY $xzr
20 $x4 = COPY $xzr
21 $x5 = COPY $xzr
22 $x6 = COPY $xzr
23 $x7 = COPY $xzr
24 $x8 = COPY $xzr
25 $x9 = COPY $xzr
[all …]
|
| D | falkor-hwpf-fix.mir | 6 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
27 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
48 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
69 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
90 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
111 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
132 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
156 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
158 # CHECK: $x1 = ORRXrs $xzr, $[[BASE]], 0
178 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
[all …]
|
| D | arm64-addrmode.ll | 8 ; CHECK: ldr xzr, [x0, #8]
19 ; CHECK: ldr xzr, [
29 ; CHECK: ldr xzr, [x0, #32760]
40 ; CHECK: ldr xzr, [x0, x[[NUM]]]
50 ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3]
62 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
75 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
85 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
95 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
105 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
[all …]
|
| D | ldst-opt-zr-clobber.mir | 8 # Check that write of xzr doesn't inhibit pairing of xzr stores since
13 # CHECK: STPXi $xzr, $xzr, $x0, 0
18 STRXui $xzr, $x0, 0 :: (store 8 into %ir.p)
19 dead $xzr = SUBSXri killed $x1, 0, 0, implicit-def $nzcv
21 STRXui $xzr, killed $x0, 1 :: (store 8 into %ir.p)
|
| D | machine-copy-remove.mir | 5 # CHECK-NOT: COPY $xzr
16 $x0 = COPY $xzr
32 # CHECK-NOT: COPY $xzr
43 $x0 = COPY $xzr
59 # CHECK: COPY $xzr
71 $x0 = COPY $xzr
87 # CHECK: COPY $xzr
99 $x0 = COPY $xzr
115 # CHECK: COPY $xzr
127 $x0 = COPY $xzr
[all …]
|
| D | machine-outliner.mir | 31 # CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG:[0-9]+]], 0
34 # CHECK-NEXT: $lr = ORRXri $xzr, 1
37 # CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0
40 # CHECK-NEXT: $lr = ORRXri $xzr, 1
43 # CHECK-NEXT: $lr = ORRXrs $xzr, $x[[REG]], 0
46 # CHECK-NEXT: $lr = ORRXri $xzr, 1
53 $x9 = ORRXri $xzr, 1
56 $lr = ORRXri $xzr, 1
68 $lr = ORRXri $xzr, 1
81 $lr = ORRXri $xzr, 1
[all …]
|
| D | ldst-zero.ll | 3 ; Tests to check that zero stores which are generated as STP xzr, xzr aren't
12 ; CHECK-DAG: stp x2, xzr, [x0, #8]
14 ; CHECK-DAG: str xzr, [x0]
29 ; CHECK-DAG: stp xzr, x2, [x0]
45 ; CHECK-DAG: stp x2, xzr, [x0, #8]
47 ; CHECK-DAG: str xzr, [x0]
62 ; CHECK-DAG: str xzr, [x0]
|
| /external/boringssl/linux-aarch64/crypto/test/ |
| D | trampoline-armv8.S | 116 str xzr, [x1]
138 mov x0, xzr
146 mov x1, xzr
154 mov x2, xzr
162 mov x3, xzr
170 mov x4, xzr
178 mov x5, xzr
186 mov x6, xzr
194 mov x7, xzr
202 mov x8, xzr
[all …]
|
| /external/boringssl/linux-aarch64/crypto/fipsmodule/ |
| D | armv8-mont.S | 63 subs xzr,x6,#1 // (*)
65 adc x13,x13,xzr
72 adc x7,x11,xzr
77 adc x13,x17,xzr
82 adc x13,x13,xzr
90 adc x7,x11,xzr
94 adc x13,x17,xzr
100 adc x19,xzr,xzr // upmost overflow bit
116 adc x7,x7,xzr
125 subs xzr,x6,#1 // (*)
[all …]
|
| /external/boringssl/ios-aarch64/crypto/fipsmodule/ |
| D | armv8-mont.S | 62 subs xzr,x6,#1 // (*)
64 adc x13,x13,xzr
71 adc x7,x11,xzr
76 adc x13,x17,xzr
81 adc x13,x13,xzr
89 adc x7,x11,xzr
93 adc x13,x17,xzr
99 adc x19,xzr,xzr // upmost overflow bit
115 adc x7,x7,xzr
124 subs xzr,x6,#1 // (*)
[all …]
|
| /external/capstone/suite/MC/AArch64/ |
| D | basic-a64-instructions.s.cs | 42 0x3f,0x8f,0x34,0xab = adds xzr, x25, w20, sxtb #3
44 0x5f,0xc0,0x23,0xab = adds xzr, x2, w3, sxtw
58 0x3f,0x8f,0x34,0xeb = subs xzr, x25, w20, sxtb #3
60 0x5f,0xc0,0x23,0xeb = subs xzr, x2, w3, sxtw
130 0x7f,0x04,0x40,0xb1 = adds xzr, x3, #1, lsl #12
131 0xff,0x53,0x40,0xf1 = subs xzr, sp, #20, lsl #12
132 0xdf,0xff,0x3f,0xf1 = subs xzr, x30, #4095
158 0x7f,0x00,0x05,0x8b = add xzr, x3, x5
159 0xf4,0x03,0x04,0x8b = add x20, xzr, x4
160 0xc4,0x00,0x1f,0x8b = add x4, x6, xzr
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 103 adds xzr, x25, w20, sxtb #3
105 adds xzr, x2, w3, sxtw
138 subs xzr, x25, w20, sxtb #3
140 subs xzr, x2, w3, sxtw
310 adds xzr, x3, #0x1, lsl #12 // FIXME: canonically should be cmn
317 subs xzr, sp, #20, lsl #12 // FIXME: canonically should be cmp
318 subs xzr, x30, #4095, lsl #0 // FIXME: canonically should be cmp
398 add xzr, x3, x5
399 add x20, xzr, x4
400 add x4, x6, xzr
[all …]
|
| D | arm64-aliases.s | 27 orr x2, xzr, x9
44 ands xzr, x1, x2, lsl #3
190 orr x20, xzr, #0xaaaaaaaaaaaaaaaa
198 orr x3, xzr, #0x1
200 orr x3, xzr, #0x10000
202 orr x3, xzr, #0x700000000
203 orr x3, xzr, #0x3000000000000
204 ; CHECK: orr x3, xzr, #0x1
206 ; CHECK: orr x3, xzr, #0x10000
208 ; CHECK: orr x3, xzr, #0x700000000
[all …]
|
| /external/llvm/test/MC/AArch64/ |
| D | basic-a64-instructions.s | 103 adds xzr, x25, w20, sxtb #3
105 adds xzr, x2, w3, sxtw
138 subs xzr, x25, w20, sxtb #3
140 subs xzr, x2, w3, sxtw
310 adds xzr, x3, #0x1, lsl #12 // FIXME: canonically should be cmn
317 subs xzr, sp, #20, lsl #12 // FIXME: canonically should be cmp
318 subs xzr, x30, #4095, lsl #0 // FIXME: canonically should be cmp
398 add xzr, x3, x5
399 add x20, xzr, x4
400 add x4, x6, xzr
[all …]
|
| D | arm64-aliases.s | 27 orr x2, xzr, x9
44 ands xzr, x1, x2, lsl #3
190 orr x20, xzr, #0xaaaaaaaaaaaaaaaa
198 orr x3, xzr, #0x1
200 orr x3, xzr, #0x10000
202 orr x3, xzr, #0x700000000
203 orr x3, xzr, #0x3000000000000
204 ; CHECK: orr x3, xzr, #0x1
206 ; CHECK: orr x3, xzr, #0x10000
208 ; CHECK: orr x3, xzr, #0x700000000
[all …]
|
| /external/llvm/test/CodeGen/AArch64/ |
| D | arm64-addrmode.ll | 8 ; CHECK: ldr xzr, [x{{[0-9]+}}, #8]
19 ; CHECK: ldr xzr, [
30 ; CHECK: ldr xzr, [x{{[0-9]+}}, #32760]
41 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
51 ; CHECK: ldr xzr, [x{{[0-9]+}}, x{{[0-9]+}}, lsl #3]
63 ; CHECK: ldr xzr, [x{{[0-9]+}}, x[[NUM]]]
76 ; CHECK-NEXT: ldr xzr, [x0, x[[NUM]]]
86 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
96 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
106 ; CHECK-NEXT: ldr xzr, [x0, [[REG]]]
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | whilelo.s | 10 whilelo p15.b, xzr, x0
16 whilelo p15.b, x0, xzr
34 whilelo p15.h, x0, xzr
46 whilelo p15.s, x0, xzr
64 whilelo p15.d, x0, xzr
|
| D | whilels.s | 10 whilels p15.b, xzr, x0
16 whilels p15.b, x0, xzr
34 whilels p15.h, x0, xzr
46 whilels p15.s, x0, xzr
64 whilels p15.d, x0, xzr
|
| D | whilelt.s | 10 whilelt p15.b, xzr, x0
16 whilelt p15.b, x0, xzr
34 whilelt p15.h, x0, xzr
46 whilelt p15.s, x0, xzr
64 whilelt p15.d, x0, xzr
|
| D | whilele.s | 10 whilele p15.b, xzr, x0
16 whilele p15.b, x0, xzr
34 whilele p15.h, x0, xzr
46 whilele p15.s, x0, xzr
64 whilele p15.d, x0, xzr
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | ldp-preind.predictable.txt | 16 # xzr != sp so "stp xzr, xzr, [sp, #8]!" is fine.
18 # CHECK: stp xzr, xzr, [sp, #8]!
|
| D | ldp-postind.predictable.txt | 16 # xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
18 # CHECK: stp xzr, xzr, [sp], #8
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | ldp-postind.predictable.txt | 16 # xzr != sp so "stp xzr, xzr, [sp], #8" is fine.
18 # CHECK: stp xzr, xzr, [sp], #8
|
| D | ldp-preind.predictable.txt | 16 # xzr != sp so "stp xzr, xzr, [sp, #8]!" is fine.
18 # CHECK: stp xzr, xzr, [sp, #8]!
|