| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | scvtf.s | 10 scvtf z0.h, p0/m, z0.h label
16 scvtf z0.h, p0/m, z0.s label
22 scvtf z0.h, p0/m, z0.d label
28 scvtf z0.s, p0/m, z0.s label
34 scvtf z0.s, p0/m, z0.d label
40 scvtf z0.d, p0/m, z0.s label
46 scvtf z0.d, p0/m, z0.d label
62 scvtf z5.d, p0/m, z0.d label
74 scvtf z5.d, p0/m, z0.d label
|
| D | scvtf-diagnostics.s | 3 scvtf z0.s, p0/m, z0.h label
8 scvtf z0.d, p0/m, z0.h label
17 scvtf z0.h, p8/m, z0.h label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 470 scvtf d1, w2 define
471 scvtf d1, w2, #1 define
476 scvtf d1, x2 define
477 scvtf d1, x2, #1 define
|
| D | arm64-advsimd.s | 1381 scvtf d0, d0, #2 define
|
| /external/llvm/test/MC/AArch64/ |
| D | arm64-fp-encoding.s | 470 scvtf d1, w2 define
471 scvtf d1, w2, #1 define
476 scvtf d1, x2 define
477 scvtf d1, x2, #1 define
|
| D | arm64-advsimd.s | 1381 scvtf d0, d0, #2 define
|
| /external/vixl/test/aarch64/ |
| D | test-trace-aarch64.cc | 580 __ scvtf(d31, d16); in GenerateTestSequenceFP() local
581 __ scvtf(d26, d31, 24); in GenerateTestSequenceFP() local
582 __ scvtf(d6, w16); in GenerateTestSequenceFP() local
583 __ scvtf(d5, w20, 6); in GenerateTestSequenceFP() local
584 __ scvtf(d16, x8); in GenerateTestSequenceFP() local
585 __ scvtf(d15, x8, 10); in GenerateTestSequenceFP() local
586 __ scvtf(s7, s4); in GenerateTestSequenceFP() local
587 __ scvtf(s8, s15, 14); in GenerateTestSequenceFP() local
588 __ scvtf(s29, w10); in GenerateTestSequenceFP() local
589 __ scvtf(s15, w21, 11); in GenerateTestSequenceFP() local
[all …]
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.cc | 3065 void Assembler::scvtf(const VRegister& vd, const VRegister& vn, int fbits) { in scvtf() function in vixl::aarch64::Assembler
3084 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf() function in vixl::aarch64::Assembler
|
| D | logic-aarch64.cc | 5293 LogicVRegister Simulator::scvtf(VectorFormat vform, in scvtf() function in vixl::aarch64::Simulator
|
| /external/v8/src/arm64/ |
| D | assembler-arm64.cc | 3218 void Assembler::scvtf(const VRegister& vd, const Register& rn, int fbits) { in scvtf() function in v8::internal::Assembler
|
| D | simulator-logic-arm64.cc | 4154 LogicVRegister Simulator::scvtf(VectorFormat vform, LogicVRegister dst, in scvtf() function in v8::internal::Simulator
|