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Searched refs:CLK_WR_ACCESS_PASSWORD (Results 1 – 2 of 2) sorted by relevance

/external/u-boot/arch/arm/cpu/armv7/bcm281xx/
Dclk-core.c20 #define CLK_WR_ACCESS_PASSWORD 0x00a5a501 macro
92 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
268 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
344 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()
/external/u-boot/arch/arm/cpu/armv7/bcm235xx/
Dclk-core.c20 #define CLK_WR_ACCESS_PASSWORD 0x00a5a501 macro
92 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in peri_clk_enable()
268 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in ccu_clk_enable()
344 writel(CLK_WR_ACCESS_PASSWORD, base + WR_ACCESS_OFFSET); in bus_clk_enable()