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Searched refs:FSYS1_MMC0_DIV_MASK (Results 1 – 1 of 1) sorted by relevance

/external/u-boot/arch/arm/mach-exynos/
Dclock_init_exynos5.c20 #define FSYS1_MMC0_DIV_MASK 0xff0f macro
999 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK; in emmc_boot_clk_div_set()