| /external/u-boot/board/freescale/mx53ard/ |
| D | mx53ard.c | 66 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
68 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
70 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
72 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
74 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
76 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
78 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
80 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in setup_iomux_nand()
205 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in weim_smc911x_iomux()
207 PAD_CTL_PKE | PAD_CTL_DSE_HIGH), in weim_smc911x_iomux()
[all …]
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| /external/u-boot/board/liebherr/display5/ |
| D | common.h | 10 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
14 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
18 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
31 #define ENET_PAD_CTRL_CLK ((PAD_CTL_PUS_100K_UP & ~PAD_CTL_PKE) | \
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| /external/u-boot/board/freescale/mx53smd/ |
| D | mx53smd.c | 63 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
65 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
70 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
72 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
74 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
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| /external/u-boot/arch/arm/include/asm/mach-imx/ |
| D | iomux-v3.h | 144 #define PAD_CTL_PUE (1 << 13 | PAD_CTL_PKE)
145 #define PAD_CTL_PKE (1 << 12) macro
197 #define PAD_CTL_PKE (1 << 3) macro
198 #define PAD_CTL_PUE (1 << 2 | PAD_CTL_PKE)
210 #define PAD_CTL_PKE (1 << 7) macro
211 #define PAD_CTL_PUE (1 << 6 | PAD_CTL_PKE)
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| /external/u-boot/board/gateworks/gw_ventana/ |
| D | common.h | 18 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
22 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
26 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
38 #define IRQ_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /external/u-boot/board/freescale/mx53evk/ |
| D | mx53evk.c | 123 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
125 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
130 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
132 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
134 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
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| /external/u-boot/board/kosagi/novena/ |
| D | novena_spl.c | 30 (PAD_CTL_PKE | PAD_CTL_PUE | \
35 (PAD_CTL_PKE | PAD_CTL_PUE | \
40 (PAD_CTL_PKE | PAD_CTL_PUE | \
45 (PAD_CTL_PKE | PAD_CTL_PUE | \
49 (PAD_CTL_PKE | PAD_CTL_PUE | \
58 (PAD_CTL_PKE | PAD_CTL_PUE | \
64 (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/board/ccv/xpress/ |
| D | xpress.c | 29 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
33 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /external/u-boot/board/freescale/mx53loco/ |
| D | mx53loco.c | 78 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
80 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
85 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
87 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
89 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
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| /external/u-boot/board/ge/mx53ppd/ |
| D | mx53ppd.c | 115 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
117 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
122 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
124 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
126 PAD_CTL_HYS | PAD_CTL_PKE), in setup_iomux_fec()
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| /external/u-boot/board/samtec/vining_2000/ |
| D | vining_2000.c | 36 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
39 #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | PAD_CTL_PKE | \
45 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | \
50 PAD_CTL_PKE | PAD_CTL_ODE | PAD_CTL_SPEED_MED | \
57 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_80ohm | \
61 PAD_CTL_PKE)
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| /external/u-boot/board/technexion/pico-imx6ul/ |
| D | pico-imx6ul.c | 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
39 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
44 #define OTG_ID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/board/udoo/neo/ |
| D | neo.c | 43 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
51 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
63 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
66 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
69 #define BOARD_DETECT_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/board/freescale/mx6sxsabresd/ |
| D | mx6sxsabresd.c | 31 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
35 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
50 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
52 #define WDOG_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_PKE | PAD_CTL_SPEED_MED | \
210 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
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| /external/u-boot/board/freescale/mx6sxsabreauto/ |
| D | mx6sxsabreauto.c | 32 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
43 #define ENET_RX_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
46 #define GPMI_PAD_CTRL0 (PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_100K_UP)
224 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_40ohm)
|
| /external/u-boot/board/freescale/mx6ul_14x14_evk/ |
| D | mx6ul_14x14_evk.c | 33 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
37 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
41 #define USDHC_DAT3_CD_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
45 #define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
55 PAD_CTL_PKE | PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm)
300 PAD_CTL_PKE | PAD_CTL_PUE | PAD_CTL_PUS_47K_UP | PAD_CTL_DSE_120ohm)
|
| /external/u-boot/board/logicpd/imx6/ |
| D | imx6logic.c | 30 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
34 #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/arch/arm/include/asm/arch-mx5/ |
| D | iomux-mx51.h | 29 #define MX51_ECSPI_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_HYS | \
33 #define MX51_GPIO_PAD_CTRL (PAD_CTL_DSE_HIGH | PAD_CTL_PKE | PAD_CTL_SRE_FAST)
35 #define MX51_PAD_CTRL_2 (PAD_CTL_PKE | PAD_CTL_HYS)
36 #define MX51_PAD_CTRL_4 (PAD_CTL_PKE | PAD_CTL_DVS | PAD_CTL_HYS)
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| /external/u-boot/board/grinn/liteboard/ |
| D | board.c | 32 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
36 #define USDHC_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/board/tqc/tqma6/ |
| D | tqma6_wru4.c | 40 PAD_CTL_PKE | \
142 PAD_CTL_PKE | \
|
| /external/u-boot/arch/arm/include/asm/arch-mx25/ |
| D | iomux-mx25.h | 142 MX25_PAD_NFRB__NFRB = IOMUX_PAD(0x27c, 0x084, 0x00, 0, 0, PAD_CTL_PKE),
169 MX25_PAD_D9__USBH2_PWR = IOMUX_PAD(0x298, 0x0a0, 0x06, 0, 0, PAD_CTL_PKE),
333 MX25_PAD_CSPI1_RDY__CSPI1_RDY = IOMUX_PAD(0x364, 0x16c, 0x00, 0, 0, PAD_CTL_PKE),
472 MX25_PAD_GPIO_A__USBOTG_PWR = IOMUX_PAD(0x3f0, 0x1f4, 0x02, 0, 0, PAD_CTL_PKE),
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| /external/u-boot/board/freescale/mx6ullevk/ |
| D | mx6ullevk.c | 23 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|
| /external/u-boot/board/freescale/mx51evk/ |
| D | mx51evk_video.c | 57 PAD_CTL_PKE | PAD_CTL_DSE_MAX | PAD_CTL_SRE_SLOW)); in setup_iomux_lcd()
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| /external/u-boot/board/freescale/mx6sllevk/ |
| D | mx6sllevk.c | 25 #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
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| /external/u-boot/board/freescale/mx6slevk/ |
| D | mx6slevk.c | 40 #define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
47 #define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
|