Searched refs:SDRAM (Results 1 – 25 of 82) sorted by relevance
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| /external/u-boot/board/renesas/sh7785lcr/ |
| D | README.sh7785lcr | 11 - DDR2-SDRAM 512MB
28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
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| /external/u-boot/board/Synology/ds109/ |
| D | openocd.cfg | 44 mww 0xD0001400 0x43000C30 ;# DDR SDRAM Configuration Register
46 mww 0xD0001408 0x22125551 ;# DDR SDRAM Timing (Low) Register
47 mww 0xD000140C 0x00000833 ;# DDR SDRAM Timing (High) Register
48 mww 0xD0001410 0x0000000d ;# DDR SDRAM Address Control Register
49 mww 0xD0001414 0x00000000 ;# DDR SDRAM Open Pages Control Register
50 mww 0xD0001418 0x00000000 ;# DDR SDRAM Operation Register
51 mww 0xD000141C 0x00000C62 ;# DDR SDRAM Mode Register
52 mww 0xD0001420 0x00000042 ;# DDR SDRAM Extended Mode Register
63 mww 0xD0001494 0x003C0000 ;# DDR2 SDRAM ODT Control (Low) Register
64 mww 0xD0001498 0x00000000 ;# DDR2 SDRAM ODT Control (High) REgister
[all …]
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| /external/u-boot/board/alliedtelesis/SBx81LIFKW/ |
| D | kwbimage.cfg | 35 DATA 0xffd01500 0x00000000 # SDRAM CS[0] Base address at 0x00000000
36 DATA 0xffd01504 0x07FFFFF1 # SDRAM CS[0] Size 128MiB
38 DATA 0xffd0150c 0x00FFFFF4 # SDRAM CS[1] Size, window disabled
39 DATA 0xffd01514 0x00FFFFF8 # SDRAM CS[2] Size, window disabled
40 DATA 0xffd0151c 0x00FFFFFC # SDRAM CS[3] Size, window disabled
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| /external/u-boot/doc/ |
| D | README.at91 | 14 0x20000000 - 23FFFFFF SDRAM (64 MB)
36 0x20000000 - 23FFFFFF SDRAM (64 MB)
58 0x20000000 - 23FFFFFF SDRAM (64 MB)
82 0x70000000 - 77FFFFFF SDRAM (128 MB)
98 0x20000000 - 23FFFFFF SDRAM (64 MB)
116 0x20000000 - 27FFFFFF SDRAM (128 MB)
137 0x20000000 - 3FFFFFFF SDRAM (512 MB)
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| D | README.nand-boot-ppc440 | 21 has to fit into 4kByte. It sets up the CPU and configures the SDRAM
23 loaded from NAND to SDRAM.
29 from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
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| D | README.sh7753evb | 11 - DDR3-SDRAM 512MB
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| D | README.sh7752evb | 11 - DDR3-SDRAM 512MB
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| /external/u-boot/drivers/ram/ |
| D | Kconfig | 5 This allows drivers to be provided for SDRAM and other RAM
18 setting up RAM (e.g. SDRAM / DDR) within SPL.
27 setting up RAM (e.g. SDRAM / DDR) within TPL.
30 bool "Enable STM32 SDRAM support"
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| /external/u-boot/drivers/ddr/altera/ |
| D | Kconfig | 2 bool "SoCFPGA DDR SDRAM driver"
5 Enable DDR SDRAM controller for the SoCFPGA devices.
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| /external/u-boot/arch/arm/mach-rockchip/rk3288/ |
| D | Kconfig | 30 functions. It includes 2 or 4GB of SDRAM and 16 or 32GB of
39 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
48 includes on-board eMMC and 2GB of SDRAM. Expansion connectors
57 also includes on-board eMMC and 1GB of SDRAM. Expansion connectors
66 has 1 or 2 GiB SDRAM. Expansion connectors provide access to
109 also includes on-board eMMC and 2GB of SDRAM. Expansion connectors
127 8GB eMMC and 2GB of SDRAM. Expansion connectors provide access to
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| /external/u-boot/board/keymile/km_arm/ |
| D | kwbimage_256M8_1.cfg | 88 # SDRAM initalization
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
194 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
200 # with the considered SDRAM internal delay
202 # with the considered SDRAM internal delay
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
209 # with the considered SDRAM internal delay
211 # with the considered SDRAM internal delay
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| D | kwbimage_128M16_1.cfg | 88 # SDRAM initalization
89 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
194 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
200 # with the considered SDRAM internal delay
202 # with the considered SDRAM internal delay
205 DATA 0xFFD0147c 0x00008452 # DDR2 SDRAM Timing High
209 # with the considered SDRAM internal delay
211 # with the considered SDRAM internal delay
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| D | kwbimage-memphis.cfg | 45 DATA 0xFFD01400 0x430004E0 # SDRAM Configuration Register
131 DATA 0xFFD01428 0x00084520 # DDR2 SDRAM Timing Low
139 DATA 0xFFD0147c 0x00008451 # DDR2 SDRAM Timing High
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| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/doc/ |
| D | README.soc | 21 - One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
65 - 1 64-bit DDR4 SDRAM memory controller with ECC
92 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
93 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
135 - One 16-bit DDR3L SDRAM memory controller, Up to 1.0 GT/s, Supports
177 - One 64-bit DDR4 SDRAM memory controllers with ECC and interleaving
219 - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
220 - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
258 b) No 32-bit DDR3 SDRAM memory
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| /external/u-boot/board/google/ |
| D | Kconfig | 16 SDRAM. It has a Panther Point platform controller hub, PCIe
37 Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a
48 LPDDR3 SDRAM. It has PCIe WiFi and Bluetooth. It also includes a
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| /external/u-boot/doc/device-tree-bindings/clock/ |
| D | rockchip,rk3288-dmc.txt | 52 -rockchip,num-channels: number of SDRAM channels (1 or 2)
53 -rockchip,pctl-timing: parameters for the SDRAM setup, in this order:
93 -rockchip,sdram-channel: SDRAM channel information, each 8 bits. Both channels
103 - rockchip,sdram-params: SDRAM base parameters, in this order:
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| /external/u-boot/doc/SPI/ |
| D | README.ti_qspi_flash | 20 execute it after storing it in SDRAM. Then, the MLO will read
21 u-boot.img from flash and execute it from SDRAM.
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| /external/u-boot/board/sbc8548/ |
| D | README | 6 memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e,
72 There is a hardware errata, which causes the older local bus SDRAM
83 the back of the PCB behind the DDR SDRAM SODIMM connector.
192 is jumpered parallel to the LBC-SDRAM, then /CS0 is for the
254 f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB)
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| /external/u-boot/board/freescale/ls1012ardb/ |
| D | README | 21 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
62 - 16-bit, 1 GB DDR3L SDRAM memory, running at data rates up to 1 GT/s
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| /external/u-boot/drivers/ram/stm32mp1/ |
| D | Kconfig | 11 the SDRAM parameters for controleur and phy need to be provided
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| /external/u-boot/arch/arm/mach-rockchip/rk3188/ |
| D | Kconfig | 8 Ethernet, It also includes on-board nand and 1GB of SDRAM.
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| /external/u-boot/board/cobra5272/bdm/ |
| D | cobra5272_uboot.gdb | 104 # CS7 -- SDRAM
119 # Dummy write to start SDRAM
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| /external/u-boot/arch/x86/ |
| D | Kconfig | 317 bool "Perform a simple RAM test after SDRAM initialisation"
319 If there is something wrong with SDRAM then the platform will
321 very simple RAM test that quickly checks whether the SDRAM seems
347 to set up SDRAM and other chipset specific initialization.
350 SDRAM so will not boot.
428 It is a binary blob which U-Boot uses to set up SDRAM.
431 SDRAM so will not boot.
441 SDRAM init run faster.
460 available at this address and can be used temporarily until SDRAM
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| /external/u-boot/board/armltd/integrator/ |
| D | README | 18 SDRAM
21 CMs may be fitted with varying amounts of SDRAM using a DIMM socket.
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| /external/u-boot/board/freescale/ls1021atwr/ |
| D | README | 36 - One DDR3L/DDR4 SDRAM memory controller with x8/x16/x32-bit configuration
81 - Supports one DDR3LP SDRAM.
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