Searched refs:SP_REG (Results 1 – 11 of 11) sorted by relevance
| /external/elfutils/backends/ |
| D | ppc64_unwind.c | 36 #define SP_REG 1 macro
56 if (! getfunc (SP_REG, 1, &sp, arg)) in EBLHOOK()
71 setfunc(SP_REG, 1, &newSp, arg); in EBLHOOK()
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| D | aarch64_unwind.c | 36 #define SP_REG 31 macro
62 if (!getfunc(SP_REG, 1, &sp, arg)) in EBLHOOK()
78 setfunc(SP_REG, 1, &newSp, arg); in EBLHOOK()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/ |
| D | local-stack-frame.ll | 23 ; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0;
24 ; PTX32: st.local.u32 [%r[[SP_REG]]], %r{{[0-9]+}};
28 ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
29 ; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}};
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| D | call-with-alloca-buffer.ll | 27 ; CHECK: add.u64 %rd[[SP_REG:[0-9]+]], %SP, 0
53 ; CHECK-NEXT: st.param.b64 [param1+0], %rd[[SP_REG]]
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| /external/llvm/test/CodeGen/NVPTX/ |
| D | local-stack-frame.ll | 23 ; PTX32: add.u32 %r[[SP_REG:[0-9]+]], %SPL, 0;
24 ; PTX32: st.local.u32 [%r[[SP_REG]]], %r{{[0-9]+}};
28 ; PTX64: add.u64 %rd[[SP_REG:[0-9]+]], %SPL, 0;
29 ; PTX64: st.local.u32 [%rd[[SP_REG]]], %r{{[0-9]+}};
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| D | call-with-alloca-buffer.ll | 29 ; CHECK: cvta.local.u64 %rd[[SP_REG:[0-9]+]]
55 ; CHECK-NEXT: st.param.b64 [param1+0], %rd[[SP_REG]]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIMachineFunctionInfo.h | 98 unsigned StackPtrOffsetReg = AMDGPU::SP_REG;
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| D | SIFrameLowering.cpp | 163 assert(MFI->getStackPtrOffsetReg() == AMDGPU::SP_REG); in getReservedPrivateSegmentWaveByteOffsetReg()
255 if (SPReg != AMDGPU::SP_REG) { in emitEntryFunctionPrologue()
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| D | SIRegisterInfo.td | 50 def SP_REG : SIReg<"", 0>;
402 (add FP_REG, SP_REG, SCRATCH_WAVE_OFFSET_REG)> {
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| D | SIISelLowering.cpp | 8428 MRI.replaceRegWith(AMDGPU::SP_REG, Info->getStackPtrOffsetReg()); in finalizeLowering()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/InstPrinter/ |
| D | AMDGPUInstPrinter.cpp | 315 case AMDGPU::SP_REG: in printRegOperand()
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