Searched refs:accesses (Results 1 – 25 of 438) sorted by relevance
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| /external/compiler-rt/lib/tsan/rtl/ |
| D | tsan_flags.inc | 42 "Report races between atomic and plain memory accesses.")
66 "Per-thread history size, controls how many previous memory accesses "
68 "history_size=0 amounts to 32K memory accesses. Each next value doubles "
69 "the amount of memory accesses, up to history_size=7 that amounts to "
70 "4M memory accesses. The default value is 2 (128K memory accesses).")
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| /external/v8/tools/clang/blink_gc_plugin/tests/ |
| D | destructor_access_finalized_field.txt | 1 destructor_access_finalized_field.cpp:18:9: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
7 destructor_access_finalized_field.cpp:19:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
13 destructor_access_finalized_field.cpp:20:5: warning: [blink-gc] Finalizer '~HeapObject' accesses po…
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| D | destructor_eagerly_finalized.txt | 1 …cpp:26:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
7 …cpp:27:5: warning: [blink-gc] Finalizer '~HeapObjectEagerFinalizedAlso' accesses eagerly finalized…
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| /external/u-boot/doc/ |
| D | README.unaligned-memory-access.txt | 9 unaligned accesses, why you need to write code that doesn't cause them,
16 Unaligned memory accesses occur when you try to read N bytes of data starting
53 - Some architectures are able to perform unaligned memory accesses
55 - Some architectures raise processor exceptions when unaligned accesses
58 - Some architectures raise processor exceptions when unaligned accesses
66 memory accesses to happen, your code will not work correctly on certain
97 to pad structures so that accesses to fields are suitably aligned (assuming
130 lead to unaligned accesses when accessing fields that do not satisfy
177 Here is another example of some code that could cause unaligned accesses:
185 This code will cause unaligned accesses every time the data parameter points
[all …]
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| D | README.fsl_iim | 28 Read operations are implemented as read accesses to the shadow registers,
42 Override operations are implemented as write accesses to the shadow
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| D | README.mxc_ocotp | 31 Read operations are implemented as read accesses to the shadow registers,
45 Override operations are implemented as write accesses to the shadow
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/SystemZ/ |
| D | unaligned-01.ll | 1 ; Check that unaligned accesses are allowed in general. We check the
22 ; Check that unaligned 2-byte accesses are allowed.
33 ; Check that unaligned 4-byte accesses are allowed.
47 ; Check that unaligned 8-byte accesses are allowed.
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| /external/llvm/test/CodeGen/SystemZ/ |
| D | unaligned-01.ll | 1 ; Check that unaligned accesses are allowed in general. We check the
25 ; Check that unaligned 2-byte accesses are allowed.
36 ; Check that unaligned 4-byte accesses are allowed.
50 ; Check that unaligned 8-byte accesses are allowed.
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| /external/llvm/test/CodeGen/X86/ |
| D | slow-unaligned-mem.ll | 1 ; Intel chips with slow unaligned memory accesses
15 ; Intel chips with fast unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
39 ; AMD chips with fast unaligned memory accesses
50 ; Other chips with slow unaligned memory accesses
58 ; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/ |
| D | slow-unaligned-mem.ll | 1 ; Intel chips with slow unaligned memory accesses
15 ; Intel chips with fast unaligned memory accesses
27 ; AMD chips with slow unaligned memory accesses
39 ; AMD chips with fast unaligned memory accesses
51 ; Other chips with slow unaligned memory accesses
59 ; Also verify that SSE4.2 or SSE4a imply fast unaligned accesses.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Analysis/LoopAccessAnalysis/ |
| D | memcheck-wrapping-pointers.ll | 1 ; RUN: opt -basicaa -loop-accesses -analyze < %s | FileCheck %s
11 ; If accesses to a and b can alias, we need to emit a run-time alias check
12 ; between accesses to a and b. However, when i and i + 1 can wrap, their
17 ; The accesses at b[i] and a[i+1] correspond to the addresses %arrayidx and
35 ; CHECK-NEXT: Grouped accesses:
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| D | nullptr.ll | 1 ; RUN: opt -loop-accesses -analyze %s | FileCheck %s
4 ; Test that the loop accesses are proven safe in this case.
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| D | independent-interleaved.ll | 1 ; RUN: opt < %s -store-to-load-forwarding-conflict-detection=false -loop-accesses -analyze | FileCh…
4 ; This test checks that we prove the strided accesses to be independent before
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| D | pr31098.ll | 1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
7 ; statically. Due to the non-unit stride of the accesses in this testcase
12 ; dependence distances between the 8 real/imaginary accesses below:
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| D | number-of-memchecks.ll | 1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
63 ; memory checks of accesses which differ by a constant value.
97 ; CHECK-NEXT: Grouped accesses:
152 ; accesses, so we cannot overflow the GEPs.
169 ; CHECK-NEXT: Grouped accesses:
248 ; CHECK-NEXT: Grouped accesses:
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| D | memcheck-off-by-one-error.ll | 1 ; RUN: opt -analyze --loop-accesses %s | FileCheck %s
3 ; This test verifies run-time boundary check of memory accesses.
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopVectorize/ |
| D | pr31098.ll | 2 …dth=4 -force-vector-interleave=1 -enable-interleaved-mem-accesses=true -debug-only=loop-accesses <…
7 ; statically. Due to the non-unit stride of the accesses in this testcase
12 ; dependence distances between the 8 real/imaginary accesses below:
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| /external/selinux/python/sepolgen/src/sepolgen/ |
| D | audit.py | 180 self.accesses = []
200 self.accesses.append(recs[i])
255 access_tuple = tuple( self.accesses)
261 self.type, self.data = audit2why.analyze(scontext, tcontext, self.tclass, self.accesses)
271 raise ValueError("Invalid permission %s\n" % " ".join(self.accesses))
535 avc.tclass] + avc.accesses)
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| /external/selinux/python/sepolgen/tests/ |
| D | test_audit.py | 78 self.assertEqual(avc.accesses, [])
96 self.assertEqual(avc.accesses, ["getattr"])
142 self.assertEqual(avc.accesses, ["read"])
166 self.assertEqual(avc.accesses, ["dac_read_search"])
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| /external/mesa3d/src/gallium/drivers/vc4/ |
| D | vc4_qpu.c | 270 int accesses = 0; in qpu_num_sf_accesses() local
295 accesses++; in qpu_num_sf_accesses()
297 accesses++; in qpu_num_sf_accesses()
301 accesses++; in qpu_num_sf_accesses()
304 accesses++; in qpu_num_sf_accesses()
312 accesses++; in qpu_num_sf_accesses()
315 return accesses; in qpu_num_sf_accesses()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoadStoreVectorizer/X86/ |
| D | merge-tbaa.ll | 4 ; The GPU Load & Store Vectorizer may merge differently-typed accesses into a
6 ; accesses correctly.
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| /external/llvm/test/Analysis/LoopAccessAnalysis/ |
| D | nullptr.ll | 1 ; RUN: opt -loop-accesses -analyze %s | FileCheck %s
4 ; Test that the loop accesses are proven safe in this case.
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| D | independent-interleaved.ll | 1 ; RUN: opt < %s -store-to-load-forwarding-conflict-detection=false -loop-accesses -analyze | FileCh…
4 ; This test checks that we prove the strided accesses to be independent before
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| D | number-of-memchecks.ll | 1 ; RUN: opt -loop-accesses -analyze < %s | FileCheck %s
63 ; memory checks of accesses which differ by a constant value.
97 ; CHECK-NEXT: Grouped accesses:
152 ; accesses, so we cannot overflow the GEPs.
169 ; CHECK-NEXT: Grouped accesses:
248 ; CHECK-NEXT: Grouped accesses:
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| /external/arm-neon-tests/ |
| D | InitCache.s | 33 ;ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
34 ORR r0, r0, #(0x1 << 4) ;Enables speculative accesses on AXI
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