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Searched refs:b0011 (Results 1 – 25 of 41) sorted by relevance

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/external/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td233 def : TLBI<"VMALLE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b000, 0>;
234 def : TLBI<"ALLE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b000, 0>;
235 def : TLBI<"ALLE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b000, 0>;
236 def : TLBI<"VAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b001>;
237 def : TLBI<"VAE2IS", 0b01, 0b100, 0b1000, 0b0011, 0b001>;
238 def : TLBI<"VAE3IS", 0b01, 0b110, 0b1000, 0b0011, 0b001>;
239 def : TLBI<"ASIDE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b010>;
240 def : TLBI<"VAAE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b011>;
241 def : TLBI<"ALLE1IS", 0b01, 0b100, 0b1000, 0b0011, 0b100, 0>;
242 def : TLBI<"VALE1IS", 0b01, 0b000, 0b1000, 0b0011, 0b101>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64SystemOperands.td338 def : TLBI<"VMALLE1IS", 0b000, 0b1000, 0b0011, 0b000, 0>;
339 def : TLBI<"ALLE2IS", 0b100, 0b1000, 0b0011, 0b000, 0>;
340 def : TLBI<"ALLE3IS", 0b110, 0b1000, 0b0011, 0b000, 0>;
341 def : TLBI<"VAE1IS", 0b000, 0b1000, 0b0011, 0b001>;
342 def : TLBI<"VAE2IS", 0b100, 0b1000, 0b0011, 0b001>;
343 def : TLBI<"VAE3IS", 0b110, 0b1000, 0b0011, 0b001>;
344 def : TLBI<"ASIDE1IS", 0b000, 0b1000, 0b0011, 0b010>;
345 def : TLBI<"VAAE1IS", 0b000, 0b1000, 0b0011, 0b011>;
346 def : TLBI<"ALLE1IS", 0b100, 0b1000, 0b0011, 0b100, 0>;
347 def : TLBI<"VALE1IS", 0b000, 0b1000, 0b0011, 0b101>;
[all …]
DAArch64SVEInstrInfo.td131 defm FSUBR_ZPmZ : sve_fp_2op_p_zds<0b0011, "fsubr">;
253 def SEL_PPPP : sve_int_pred_log<0b0011, "sel">;
282 defm LD1B_D_IMM : sve_mem_cld_si<0b0011, "ld1b", Z_d, ZPR64>;
328 defm LD1B_D : sve_mem_cld_ss<0b0011, "ld1b", Z_d, ZPR64, GPR64NoXZRshifted8>;
346 defm LDNF1B_D_IMM : sve_mem_cldnf_si<0b0011, "ldnf1b", Z_d, ZPR64>;
364 defm LDFF1B_D : sve_mem_cldff_ss<0b0011, "ldff1b", Z_d, ZPR64, GPR64shifted8>;
411 …defm GLDFF1B_S : sve_mem_32b_gld_vs_32_unscaled<0b0011, "ldff1b", ZPR32ExtSXTW8Only, ZPR32ExtUXT…
433 defm GLDFF1B_S : sve_mem_32b_gld_vi_32_ptrs<0b0011, "ldff1b", imm0_31>;
446 defm GLDFF1B_D : sve_mem_64b_gld_vi_64_ptrs<0b0011, "ldff1b", imm0_31>;
463 defm GLDFF1B_D : sve_mem_64b_gld_vs2_64_unscaled<0b0011, "ldff1b">;
[all …]
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg164 # bit19-16: 0b0011, (write) M_ODT[0] is asserted during write to DRAM CS0 and CS1
174 # bit3-0: 0b0011, internal ODT is asserted during read from DRAM bank 0-1
/external/llvm/lib/Target/Sparc/
DSparcInstrAliases.td276 defm : int_cond_alias<"l", 0b0011>;
300 defm : fp_cond_alias<"ul", 0b0011>;
323 defm : cp_cond_alias<"13", 0b0011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/
DSparcInstrAliases.td276 defm : int_cond_alias<"l", 0b0011>;
300 defm : fp_cond_alias<"ul", 0b0011>;
323 defm : cp_cond_alias<"13", 0b0011>;
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lschl.cfg183 # bit23-20: 0b0011, (write) M_ODT[1] is asserted during write to DRAM CS0, CS1
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfoV4.td261 let Inst{27-24} = 0b0011;
302 let Inst{27-24} = 0b0011;
425 def L4_loadbzw2_ap : T_LD_abs_set <"memubh", IntRegs, 0b0011>;
483 def L4_loadbzw2_ur : T_LoadAbsReg<"memubh", "LDriubh2", IntRegs, 0b0011>;
547 let IClass = 0b0011;
579 let IClass = 0b0011;
869 let IClass = 0b0011;
904 let IClass = 0b0011;
933 let IClass = 0b0011;
964 let IClass = 0b0011;
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DHexagonInstrInfoV3.td101 : T_ALU64_rr<"add", suffix, 0b0011, 0b011, MinOp, 0, 0, "">;
DHexagonInstrInfo.td682 let Inst{27-24} = 0b0011;
868 let Inst{27-24} = 0b0011;
989 def A2_vcmpheq : T_vcmp <"vcmph.eq", 0b0011>;
1289 : T_ALU64_rr<mnemonic, !if(IsSat,":sat",""), 0b0011, MajOp, MinOp, OpsRev,
1300 : T_ALU64_rr<mnemonic, "", 0b0011, 0b111, MinOp, OpsRev, IsComm,
1745 def L2_loadbzw2_io: T_load_io<"memubh", IntRegs, 0b0011, s11_1Ext>;
1944 def L2_loadbzw2_pi : T_load_pi <"memubh", IntRegs, s4_1Imm, 0b0011>;
2019 def L2_loadbzw2_pr : T_load_pr <"memubh", IntRegs, 0b0011, HalfWordAccess>;
2082 def L2_loadbzw2_pcr : T_load_pcr <"memubh", IntRegs, 0b0011>;
2166 def L2_loadbzw2_pci : T_load_pci <"memubh", IntRegs, s4_1Imm, 0b0011>;
[all …]
DHexagonInstrEnc.td822 class V6_vasrwhsat_enc : Enc_COPROC_VX_4op_r<0b0011>;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrNEON.td354 : NLdSt<0, 0b10, 0b0011, op7_4,
389 : NLdSt<0, 0b10, 0b0011, op7_4,
809 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
850 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1248 : NLdSt<0, 0b00, 0b0011, op7_4, (outs),
1283 : NLdSt<0, 0b00, 0b0011, op7_4, (outs GPR:$wb),
1702 def VST4LNd8 : VST4LN<0b0011, {?,?,?,?}, "8"> {
1741 def VST4LNd8_UPD : VST4LNWB<0b0011, {?,?,?,?}, "8"> {
3563 defm VQDMLALsl: N3VLInt3SL_HS<0, 0b0011, "vqdmlal", "s", int_arm_neon_vqdmlal>;
3637 defm VSUBWs : N3VW_QHS<0,1,0b0011,0, "vsubw", "s", sub, sext, 0>;
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DARMInstrVFP.td411 def VCVTBHS: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
422 def VCVTTHS: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
DARMInstrInfo.td3105 defm RSB : AsI1_rbin_irs <0b0011, "rsb",
3111 defm RSBS : AsI1_rbin_s_is<0b0011, "rsb",
3574 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
3586 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
3799 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
3804 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4594 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, so_imm:$a), NoItinerary,
/external/llvm/lib/Target/ARM/
DARMInstrNEON.td838 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
840 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
842 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
876 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
878 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
880 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
1290 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1331 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1825 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1827 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
[all …]
DARMInstrVFP.td672 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
682 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
699 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
726 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
DARMInstrInfo.td3495 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
3990 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4002 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4222 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4228 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
5255 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrNEON.td860 def VLD2q8 : VLD2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2,
862 def VLD2q16 : VLD2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2,
864 def VLD2q32 : VLD2<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2,
898 defm VLD2q8wb : VLD2WB<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VLD2x2u,
900 defm VLD2q16wb : VLD2WB<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VLD2x2u,
902 defm VLD2q32wb : VLD2WB<0b0011, {1,0,?,?}, "32", VecListFourD, IIC_VLD2x2u,
1331 def VLD4LNd8 : VLD4LN<0b0011, {?,?,?,?}, "8"> {
1372 def VLD4LNd8_UPD : VLD4LNWB<0b0011, {?,?,?,?}, "8"> {
1913 def VST2q8 : VST2<0b0011, {0,0,?,?}, "8", VecListFourD, IIC_VST2x2,
1915 def VST2q16 : VST2<0b0011, {0,1,?,?}, "16", VecListFourD, IIC_VST2x2,
[all …]
DARMInstrVFP.td690 def VCVTBSH: ASuI<0b11101, 0b11, 0b0011, 0b01, 0, (outs SPR:$Sd), (ins SPR:$Sm),
707 def VCVTTSH: ASuI<0b11101, 0b11, 0b0011, 0b11, 0, (outs SPR:$Sd), (ins SPR:$Sm),
732 def VCVTBDH : ADuI<0b11101, 0b11, 0b0011, 0b01, 0,
765 def VCVTTDH : ADuI<0b11101, 0b11, 0b0011, 0b11, 0,
DARMInstrInfo.td3627 defm RSB : AsI1_rbin_irs<0b0011, "rsb",
4176 def SMMULR : AMul2I <0b0111010, 0b0011, (outs GPR:$Rd), (ins GPR:$Rn, GPR:$Rm),
4191 def SMMLAR : AMul2Ia <0b0111010, 0b0011, (outs GPR:$Rd),
4471 def RBIT : AMiscA1I<0b01101111, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
4477 def REV : AMiscA1I<0b01101011, 0b0011, (outs GPR:$Rd), (ins GPR:$Rm),
5533 def MSRi : ABI<0b0011, (outs), (ins msr_mask:$mask, mod_imm:$imm), NoItinerary,
/external/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td594 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
595 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
596 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
652 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
653 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
658 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
659 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
673 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
674 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsMSAInstrInfo.td592 class COPY_U_B_ENC : MSA_ELM_COPY_B_FMT<0b0011, 0b011001>;
593 class COPY_U_H_ENC : MSA_ELM_COPY_H_FMT<0b0011, 0b011001>;
594 class COPY_U_W_ENC : MSA_ELM_COPY_W_FMT<0b0011, 0b011001>;
650 class FCNE_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011100>;
651 class FCNE_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011100>;
656 class FCUEQ_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011010>;
657 class FCUEQ_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011010>;
671 class FDIV_W_ENC : MSA_3RF_FMT<0b0011, 0b0, 0b011011>;
672 class FDIV_D_ENC : MSA_3RF_FMT<0b0011, 0b1, 0b011011>;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVInstrInfo.td362 let imm12 = {0b1000,0b0011,0b0011};
/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/
DCellSDKIntrinsics.td65 RRRForm<0b0011, (outs VECREG:$rT), (ins VECREG:$rA, VECREG:$rB, VECREG:$rC),
/external/deqp/external/vulkancts/modules/vulkan/conditional_rendering/
DvktConditionalDrawAndClearTests.cpp130 b0011 = 0x3, enumerator

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