| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/ |
| D | fcadd.s | 10 fcadd z0.h, p0/m, z0.h, z0.h, #90 label
16 fcadd z0.s, p0/m, z0.s, z0.s, #90 label
22 fcadd z0.d, p0/m, z0.d, z0.d, #90 label
28 fcadd z31.h, p7/m, z31.h, z31.h, #270 label
34 fcadd z31.s, p7/m, z31.s, z31.s, #270 label
40 fcadd z31.d, p7/m, z31.d, z31.d, #270 label
56 fcadd z4.d, p7/m, z4.d, z31.d, #270 label
68 fcadd z4.d, p7/m, z4.d, z31.d, #270 label
|
| D | fcadd-diagnostics.s | 6 fcadd z0.d, p2/m, z1.d, z2.d, #90 label
15 fcadd z0.d, p8/m, z0.d, z1.d, #90 label
24 fcadd z0.d, p0/m, z0.d, z1.d, #0 label
29 fcadd z0.d, p0/m, z0.d, z1.d, #180 label
34 fcadd z0.d, p0/m, z0.d, z1.d, #450 label
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | armv8.3a-complex.s | 52 fcadd v0.4h, v1.4h, v2.4h, #90
56 fcadd v0.8h, v1.8h, v2.8h, #90
60 fcadd v0.2s, v1.2s, v2.2s, #90
63 fcadd v0.4s, v1.4s, v2.4s, #90
66 fcadd v0.2d, v1.2d, v2.2d, #90
71 fcadd v0.2s, v1.2s, v2.2s, #90
74 fcadd v0.2s, v1.2s, v2.2s, #270
79 fcadd v0.2s, v1.2s, v2.2s, #1
81 fcadd v0.2s, v1.2s, v2.2s, #360
83 fcadd v0.2s, v1.2s, v2.2s, #-90
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.3a-complex.txt | 42 # FP16: fcadd v0.4h, v1.4h, v2.4h, #90
46 # FP16: fcadd v0.8h, v1.8h, v2.8h, #90
50 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
53 # CHECK: fcadd v0.4s, v1.4s, v2.4s, #90
56 # CHECK: fcadd v0.2d, v1.2d, v2.2d, #90
61 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #90
64 # CHECK: fcadd v0.2s, v1.2s, v2.2s, #270
|
| /external/vixl/src/aarch64/ |
| D | logic-aarch64.cc | 2234 LogicVRegister Simulator::fcadd(VectorFormat vform, in fcadd() function in vixl::aarch64::Simulator
2270 LogicVRegister Simulator::fcadd(VectorFormat vform, in fcadd() function in vixl::aarch64::Simulator
2278 fcadd<float>(vform, dst, src1, src2, rot); in fcadd()
2281 fcadd<double>(vform, dst, src1, src2, rot); in fcadd()
|
| D | simulator-aarch64.h | 2222 LogicVRegister fcadd(VectorFormat vform,
2227 LogicVRegister fcadd(VectorFormat vform,
|
| D | assembler-aarch64.h | 3493 void fcadd(const VRegister& vd,
|
| D | macro-assembler-aarch64.h | 2921 fcadd(vd, vn, vm, rot); in Fcadd()
|
| D | simulator-aarch64.cc | 4478 fcadd(vf, rd, rn, rm, rot); in VisitNEON3SameExtra()
|
| D | assembler-aarch64.cc | 3723 void Assembler::fcadd(const VRegister& vd, in fcadd() function in vixl::aarch64::Assembler
|
| /external/vixl/test/aarch64/ |
| D | test-cpu-features-aarch64.cc | 3469 TEST_FP_FCMA_NEON(fcadd_0, fcadd(v0.V2S(), v1.V2S(), v2.V2S(), 270))
3470 TEST_FP_FCMA_NEON(fcadd_1, fcadd(v0.V4S(), v1.V4S(), v2.V4S(), 90))
3471 TEST_FP_FCMA_NEON(fcadd_2, fcadd(v0.V2D(), v1.V2D(), v2.V2D(), 270))
3675 TEST_FP_FCMA_NEON_NEONHALF(fcadd_0, fcadd(v0.V4H(), v1.V4H(), v2.V4H(), 90))
3676 TEST_FP_FCMA_NEON_NEONHALF(fcadd_1, fcadd(v0.V8H(), v1.V8H(), v2.V8H(), 90))
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SVEInstrInfo.td | 151 defm FCADD_ZPmZ : sve_fp_fcadd<"fcadd">;
|
| D | AArch64InstrInfo.td | 515 "fcadd", null_frag>;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11842 "a\005faddp\005faddv\005fcadd\005fccmp\006fccmpe\005fcmeq\005fcmge\005fc"
12854 …{ 994 /* fcadd */, AArch64::FCADDv2f64, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4…
12855 …{ 994 /* fcadd */, AArch64::FCADDv4f32, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4…
12856 …{ 994 /* fcadd */, AArch64::FCADDv8f16, Convert__VectorReg1281_0__VectorReg1281_2__VectorReg1281_4…
12857 …{ 994 /* fcadd */, AArch64::FCADDv2f32, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__C…
12858 …{ 994 /* fcadd */, AArch64::FCADDv4f16, Convert__VectorReg641_0__VectorReg641_2__VectorReg641_4__C…
12859 …{ 994 /* fcadd */, AArch64::FCADD_ZPmZ_H, Convert__SVEVectorHReg1_0__SVEPredicate3bAnyReg1_1__Tie0…
12860 …{ 994 /* fcadd */, AArch64::FCADD_ZPmZ_S, Convert__SVEVectorSReg1_0__SVEPredicate3bAnyReg1_1__Tie0…
12861 …{ 994 /* fcadd */, AArch64::FCADD_ZPmZ_D, Convert__SVEVectorDReg1_0__SVEPredicate3bAnyReg1_1__Tie0…
19323 …{ 994 /* fcadd */, AArch64::FCADDv2f64, Convert__VectorReg1281_1__VectorReg1281_2__VectorReg1281_3…
[all …]
|
| /external/vixl/doc/aarch64/ |
| D | supported-instructions-aarch64.md | 1676 void fcadd(const VRegister& vd,
|