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Searched refs:getOutRegs (Results 1 – 4 of 4) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.h165 std::set<unsigned> &getOutRegs() { return LiveOutRegs; } in getOutRegs() function
481 std::set<unsigned> getOutRegs() { in getOutRegs() function
DSIMachineScheduler.cpp1475 std::set<unsigned> PredOutRegs = Pred->getOutRegs(); in SIScheduleBlockScheduler()
1517 for (unsigned Reg : DAG->getOutRegs()) { in SIScheduleBlockScheduler()
1522 const std::set<unsigned> &OutRegs = Block->getOutRegs(); in SIScheduleBlockScheduler()
1539 std::set<unsigned> PredOutRegs = Pred->getOutRegs(); in SIScheduleBlockScheduler()
1651 TryCand.Block->getOutRegs())[DAG->getVGPRSetID()]; in pickBlock()
1730 addLiveRegs(Block->getOutRegs()); in blockScheduled()
/external/llvm/lib/Target/AMDGPU/
DSIMachineScheduler.cpp1319 std::set<unsigned> PredOutRegs = Pred->getOutRegs(); in SIScheduleBlockScheduler()
1371 std::set<unsigned> PredOutRegs = Pred->getOutRegs(); in SIScheduleBlockScheduler()
1490 TryCand.Block->getOutRegs())[DAG->getVGPRSetID()]; in pickBlock()
1575 addLiveRegs(Block->getOutRegs()); in blockScheduled()
DSIMachineScheduler.h157 std::set<unsigned> &getOutRegs() { return LiveOutRegs; } in getOutRegs() function