Home
last modified time | relevance | path

Searched refs:iops (Results 1 – 25 of 36) sorted by relevance

12

/external/llvm/lib/Target/ARM/
DARMInstrFormats.td352 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
356 let InOperandList = iops;
363 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
364 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
365 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
366 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
367 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
368 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
369 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
370 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
[all …]
DARMInstrThumb2.td295 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
297 : T2I<oops, iops, itin, opc, asm, pattern> {
308 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
310 : T2sI<oops, iops, itin, opc, asm, pattern> {
321 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
323 : T2I<oops, iops, itin, opc, asm, pattern> {
334 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
336 : T2I<oops, iops, itin, opc, asm, pattern> {
347 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
349 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrThumb.td837 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
839 : T1pI<oops, iops, itin, opc, asm, pattern>,
846 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
848 : T1pI<oops, iops, itin, opc, asm, pattern>,
857 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
859 : T1sI<oops, iops, itin, opc, asm, pattern>,
866 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
868 : T1sI<oops, iops, itin, opc, asm, pattern>,
877 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
879 : T1sI<oops, iops, itin, opc, asm, pattern>,
[all …]
DARMInstrVFP.td1201 bits<4> opcod4, dag oops, dag iops,
1204 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1220 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1222 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1236 bits<4> opcod4, dag oops, dag iops,
1239 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1335 bits<4> opcod4, dag oops, dag iops,
1338 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1354 bits<4> opcod4, dag oops, dag iops,
1357 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all …]
DARMInstrInfo.td1960 class CPS<dag iops, string asm_ops>
1961 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
3541 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3543 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3823 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3825 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3833 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3835 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3845 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3847 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMInstrFormats.td293 class PseudoInst<dag oops, dag iops, InstrItinClass itin, list<dag> pattern>
297 let InOperandList = iops;
304 class ARMPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
306 : PseudoInst<oops, iops, itin, pattern> {
312 class tPseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
314 : PseudoInst<oops, iops, itin, pattern> {
320 class t2PseudoInst<dag oops, dag iops, int sz, InstrItinClass itin,
322 : PseudoInst<oops, iops, itin, pattern> {
327 class ARMPseudoExpand<dag oops, dag iops, int sz,
330 : ARMPseudoInst<oops, iops, sz, itin, pattern>,
[all …]
DARMInstrThumb2.td238 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
240 : T2I<oops, iops, itin, opc, asm, pattern> {
251 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
253 : T2sI<oops, iops, itin, opc, asm, pattern> {
264 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
266 : T2I<oops, iops, itin, opc, asm, pattern> {
277 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
279 : T2I<oops, iops, itin, opc, asm, pattern> {
290 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
292 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrThumb.td786 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
788 : T1pI<oops, iops, itin, opc, asm, pattern>,
795 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
797 : T1pI<oops, iops, itin, opc, asm, pattern>,
806 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
808 : T1sI<oops, iops, itin, opc, asm, pattern>,
815 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
817 : T1sI<oops, iops, itin, opc, asm, pattern>,
826 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
828 : T1sI<oops, iops, itin, opc, asm, pattern>,
[all …]
DARMInstrVFP.td613 bits<4> opcod4, dag oops, dag iops,
616 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
630 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
632 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
684 bits<4> opcod4, dag oops, dag iops,
687 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
701 bits<4> opcod4, dag oops, dag iops,
704 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1047 class MovFromVFP<bits<4> opc19_16, dag oops, dag iops, string opc, string asm,
1049 VFPAI<oops, iops, VFPMiscFrm, IIC_fpSTAT, opc, asm, pattern> {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMInstrFormats.td364 class AsmPseudoInst<string asm, dag iops, dag oops = (outs)>
368 let InOperandList = iops;
375 class ARMAsmPseudo<string asm, dag iops, dag oops = (outs)>
376 : AsmPseudoInst<asm, iops, oops>, Requires<[IsARM]>;
377 class tAsmPseudo<string asm, dag iops, dag oops = (outs)>
378 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb]>;
379 class t2AsmPseudo<string asm, dag iops, dag oops = (outs)>
380 : AsmPseudoInst<asm, iops, oops>, Requires<[IsThumb2]>;
381 class VFP2AsmPseudo<string asm, dag iops, dag oops = (outs)>
382 : AsmPseudoInst<asm, iops, oops>, Requires<[HasVFP2]>;
[all …]
DARMInstrThumb2.td298 class T2OneRegImm<dag oops, dag iops, InstrItinClass itin,
300 : T2I<oops, iops, itin, opc, asm, pattern> {
311 class T2sOneRegImm<dag oops, dag iops, InstrItinClass itin,
313 : T2sI<oops, iops, itin, opc, asm, pattern> {
324 class T2OneRegCmpImm<dag oops, dag iops, InstrItinClass itin,
326 : T2I<oops, iops, itin, opc, asm, pattern> {
337 class T2OneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
339 : T2I<oops, iops, itin, opc, asm, pattern> {
350 class T2sOneRegShiftedReg<dag oops, dag iops, InstrItinClass itin,
352 : T2sI<oops, iops, itin, opc, asm, pattern> {
[all …]
DARMInstrThumb.td854 class T1pIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
856 : T1pI<oops, iops, itin, opc, asm, pattern>,
863 class T1pIMiscEncode<bits<7> opA, dag oops, dag iops, InstrItinClass itin,
865 : T1pI<oops, iops, itin, opc, asm, pattern>,
874 class T1sIDPEncode<bits<4> opA, dag oops, dag iops, InstrItinClass itin,
876 : T1sI<oops, iops, itin, opc, asm, pattern>,
883 class T1sIGenEncode<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
885 : T1sI<oops, iops, itin, opc, asm, pattern>,
894 class T1sIGenEncodeImm<bits<5> opA, dag oops, dag iops, InstrItinClass itin,
896 : T1sI<oops, iops, itin, opc, asm, pattern>,
[all …]
DARMInstrVFP.td1254 bits<4> opcod4, dag oops, dag iops,
1257 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1273 bits<4> opcod4, dag oops, dag iops,InstrItinClass itin,
1275 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1289 bits<4> opcod4, dag oops, dag iops,
1292 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1400 bits<4> opcod4, dag oops, dag iops,
1403 : AVConv1I<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
1419 bits<4> opcod4, dag oops, dag iops,
1422 : AVConv1In<opcod1, opcod2, opcod3, opcod4, oops, iops, itin, opc, asm,
[all …]
DARMInstrInfo.td2067 class CPS<dag iops, string asm_ops>
2068 : AXI<(outs), iops, MiscFrm, NoItinerary, !strconcat("cps", asm_ops),
3673 dag iops = (ins GPRnopc:$Rn, GPRnopc:$Rm),
3675 : AI<(outs GPRnopc:$Rd), iops, DPFrm, IIC_iALUr, opc, asm, pattern>,
3986 class AsMul1I32<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3988 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
3996 class AsMul1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
3998 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
4008 class AsMla1I64<bits<7> opcod, dag oops, dag iops, InstrItinClass itin,
4010 : AsMul1I<opcod, oops, iops, itin, opc, asm, pattern> {
[all …]
/external/autotest/client/site_tests/platform_CryptohomeFio/
Dcontrol.stress22 'surfing': 'iops',
27 '16k_read': 'iops',
28 '16k_write': 'iops',
29 '8k_read': 'iops',
30 '8k_write': 'iops',
31 '4k_read': 'iops',
32 '4k_write': 'iops',
/external/autotest/client/site_tests/kernel_fs_Punybench/
Dkernel_fs_Punybench.py223 iops = r2.group(0)
224 self.write_perf_keyval({prefix + 'ureadrand_iops': iops})
266 iops = r2.group(0)
267 self.write_perf_keyval({prefix + 'uwriterand_iops': iops})
288 iops = r2.group(0)
289 self.write_perf_keyval({prefix + 'uwritesync_iops': iops})
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td27 class NI<dag oops, dag iops, list<dag> pattern, bit stack, string asmstr = "",
31 dag InOperandList = iops;
36 // We have 2 sets of operands (oops & iops) for the register and stack
56 multiclass NRI<dag oops, dag iops, list<dag> pattern, string asmstr = "",
58 defm "": I<oops, iops, oops, iops, pattern, asmstr, asmstr, inst>;
/external/mksh/src/
Dsyn.c271 struct ioword *iop, **iops; in get_command() local
276 iops = alloc2((NUFILE + 1), sizeof(struct ioword *), ATEMP); in get_command()
284 afree(iops, ATEMP); in get_command()
314 iops[iopn++] = iop; in get_command()
515 iops[iopn++] = iop; in get_command()
519 afree(iops, ATEMP); in get_command()
522 iops[iopn++] = NULL; in get_command()
523 iops = aresize2(iops, iopn, sizeof(struct ioword *), ATEMP); in get_command()
524 t->ioact = iops; in get_command()
/external/swiftshader/third_party/LLVM/lib/Target/PTX/
DPTXInstrFormats.td43 class InstPTX<dag oops, dag iops, string asmstr, list<dag> pattern>
46 dag InOperandList = !con(iops, (ins pred:$_p));
/external/ltp/testcases/kernel/controllers/io-throttle/
Diobw.c61 static const char *iops[] = { variable
77 * 1000000L / 1024, iops[op]); in print_results()
/external/llvm/test/Bindings/llvm-c/
Decho.ll48 define i32 @iops(i32 %a, i32 %b) {
66 %1 = call i32 @iops(i32 23, i32 19)
/external/llvm/lib/Target/WebAssembly/
DWebAssemblyInstrFormats.td24 class I<dag oops, dag iops, list<dag> pattern, string asmstr = "">
27 dag InOperandList = iops;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td46 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
49 dag InOperandList = iops;
69 class I<dag oops, dag iops, string asm, string operands, string cstr,
73 dag InOperandList = iops;
1045 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
1047 : I<oops, iops, asm, operands, "", pattern> {
1053 class SimpleSystemI<bit L, dag iops, string asm, string operands,
1055 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
1060 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
1061 : BaseSystemI<L, oops, iops, asm, operands>,
[all …]
/external/llvm/lib/Target/AArch64/
DAArch64InstrFormats.td43 class Pseudo<dag oops, dag iops, list<dag> pattern, string cstr = "">
46 dag InOperandList = iops;
58 class I<dag oops, dag iops, string asm, string operands, string cstr,
62 dag InOperandList = iops;
834 class BaseSystemI<bit L, dag oops, dag iops, string asm, string operands,
836 : I<oops, iops, asm, operands, "", pattern> {
842 class SimpleSystemI<bit L, dag iops, string asm, string operands,
844 : BaseSystemI<L, (outs), iops, asm, operands, pattern> {
849 class RtSystemI<bit L, dag oops, dag iops, string asm, string operands>
850 : BaseSystemI<L, oops, iops, asm, operands>,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/Bindings/llvm-c/
Decho.ll58 define i32 @iops(i32 %a, i32 %b) {
76 %1 = call i32 @iops(i32 23, i32 19)

12