Searched refs:postdiv2 (Results 1 – 11 of 11) sorted by relevance
| /external/u-boot/drivers/clk/rockchip/ |
| D | clk_rk3128.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
50 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
63 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
79 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
98 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
101 postdiv2 > max_postdiv2) { in pll_para_config()
108 div->postdiv2 = postdiv2; in pll_para_config()
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| D | clk_rk322x.c | 31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
53 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
66 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
202 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
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| D | clk_rk3399.c | 36 u32 postdiv2; member
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
295 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
300 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
321 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
337 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
352 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
353 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
356 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
359 postdiv2 > max_postdiv2) { in pll_para_config()
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| D | clk_rk3036.c | 34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
57 div->postdiv2, vco_hz, output_hz); in rkclk_set_pll()
68 (div->postdiv2 << PLL_POSTDIV2_SHIFT | in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
201 postdiv2 = (con & PLL_POSTDIV2_MASK) >> PLL_POSTDIV2_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| D | clk_rv1108.c | 32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
63 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
76 postdiv2 = (con1 & POSTDIV2_MASK) >> POSTDIV2_SHIFT; in rkclk_pll_get_rate()
78 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
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| D | clk_rk3328.c | 24 u32 postdiv2; member
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
247 div->postdiv2, vco_khz, output_khz); in rkclk_set_pll()
268 (div->postdiv2 << PLL_POSTDIV2_SHIFT) | in rkclk_set_pll()
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| /external/u-boot/arch/arm/include/asm/arch-rockchip/ |
| D | cru_rv1108.h | 53 u32 postdiv2; member
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| D | cru_rk3036.h | 64 u32 postdiv2; member
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| D | cru_rk3128.h | 67 u32 postdiv2; member
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| D | cru_rk322x.h | 65 u32 postdiv2; member
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| /external/u-boot/arch/arm/mach-rockchip/rk3036/ |
| D | sdram_rk3036.c | 343 (dpll_init_cfg.postdiv2 << PLL_POSTDIV2_SHIFT | in rkdclk_init()
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